Viability of configMAX_SYSCALL_INTERRUPT_PRIORITY on Cortex-M0+

Kernel
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Hi everyone,

I just had a quick question regarding configMAX_SYSCALL_INTERRUPT_PRIORITY on Cortex-M0+. I understand that this configuration option is not respected on Cortex-M0+, and I’m wondering if it is viable to support it or similar intended functionality thereof (and mind, I plead ignorance on the finer details of the Cortex-M0+ architecture).

FreeRTOS’s critical sections on Cortex-M0+ utilize PRIMASK to disable and re-enable all interrupts. This is a problem for ISRs where lack of responsiveness cannot be tolerated. On other ports (e.g., M3, M4, M33), this is not a problem as configMAX_SYSCALL_INTERRUPT_PRIORITY is respected through the BASEPRI register, which is not supported on Cortex-M0+.

Since NVIC reads and writes on Cortex-M0+ are atomic, would it be possible to take a copy of ISER, disable all interrupts that aren’t N (where N is >=1 interrupt, and N must not be disabled during a critical section), enter the critical section, perform work, and restore the state of ISER?

Am I missing something here?

Thank you,
Mike

2

Cortex-M0+ does not have BASEPRI register and therefore, we cannot the selectively mask interrupts.

The ISER (Interrupt Set-Enable Register) is used to enable or disable interrupts. It is not intended for masking interrupts. Since interrupt priorities are configured at the application level, we cannot reliably determine which interrupts to disable in order to implement a critical section. You can implement this approach in your application if ti suits your use case.