Cortex-M0+: how to choose correct interrupt priorities?

Kernel
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My project uses a STM32L073 controller, which is a Cortex-M0+ core with 4 possible interrupt priorities.

The Cortex-M0 port has no setting for configMAX_SYSCALL_INTERRUPT_PRIORITY because of the not existing BASEPRI register.
Usage of FreeRTOS-critical-sections lead (amongst others) to the CMSIS intrinsic functions __disable_irq() respective __enable_irq().
Function __disable_irq() sets bit 0 at the PRIMASK register which “Prevents the activation of all exceptions with configurable priority”.

So I would expect that it’s allowed to use FreeRTOS …FromISR() functions at any interrupt-service-routine with priority from 0…3.
If a critical-section (e.g. inside the scheduler) is active, no other interrupt can preempt it.

Is this correct?

To create my basic project code I use STs CubeMX V6.2.0 software which irritates me by allowing only the lowest interrupt-priority 3 for interrupts that use FreeRTOS functions.
But why should only interrupts with identical priority as the scheduler be allowed to call …FromISR() functions?

Can anyone clear up my confusion?

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In the M0 port critical sections are implemented with a global interrupt disable - so an interrupt cannot occur if you are within a critical section. Additionally, interrupts don’t nest, so there is no need for critical sections inside the interrupts themselves. Hence there is no configMAX_SYSCALL_INTERRUPT_PRIORITY and you can use whichever interrupt priority is best for your application’s requirements - without restriction.