ISR with lower priority than configMAX_SYSCALL_INTERRUPT_PRIORITY

tobias89 wrote on Thursday, August 28, 2014:

Hi, I am using ARM Cortex M0 with FreeRTOS v7.1.0. I am aware that any interrupt service routine that calls ISR safe FreeRTOS API functions (such as xQueueSendToBackFromISR()) must have logical priority equal or below configMAX_SYSCALL_INTERRUPT_PRIORITY (defined in FreeRTOSConfig.h), which is, in our case, defined as 5 shifted by 6 bits, which results in 1.

However, this project was before some time, when I wasn’t aware of that. I used NVIC_EnableIRQ() to enable certain interrupt routine without setting its priority, which leads to setting it to 0 (higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY).

The thing that bothers me is that it works flawlessly to this day, even though it shouldn’t (judging by the all warnings). I will correct that in the new version of project, but can somebody please explain why does it work and in which case it wouldn’t work and why?

Thank you!

rtel wrote on Thursday, August 28, 2014:

You will be fine doing that on an M0 part. It is the ARM Cortex-M3 and M4F ports (as well as some non ARM ports) where the rule you mention above applies. Even then, if you were to get it wrong, it would not fail immediately, only when a set of events happened at the same time. The newer M3 and M4F ports (yours is a little older) have lots of asserts to help people track down such issues.

Regards.

tobias89 wrote on Friday, August 29, 2014:

Thank you for the answer, that’s interesting. Could you please explain a bit why the rule doesn’t apply on M0? It supports interrupt nesting, as well as the M3.

Regards!

rtel wrote on Friday, August 29, 2014:

The M0 does not have the basepri register, so there is no clean single instruction way of masking only a subset of interrupt priorities.

Regards.

alainm3 wrote on Friday, August 29, 2014:

Please, can you point me to somewhere to study this further?

It realy sounds very important but I really didn’t understand this as
well as I should.
And CM0 is going to be an important part of our lifes, do we like it or
not…

Thanks, Alain

Em 29-08-2014 06:55, Real Time Engineers ltd. escreveu:

The M0 does not have the basepri register, so there is no clean single
instruction way of masking only a subset of interrupt priorities.

Regards.


ISR with lower priority than configMAX_SYSCALL_INTERRUPT_PRIORITY
https://sourceforge.net/p/freertos/discussion/382005/thread/ec13cb4f/?limit=25#5387


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davedoors wrote on Friday, August 29, 2014:

ARM are the guardians of the documentation on their own chips. Start here http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html (which I found using Google)

tobias89 wrote on Saturday, August 30, 2014:

This is also a good book for understanding CM0
http://caxapa.ru/thumbs/424855/The_Definitive_Guide_to_the_ARM_Cortex-M.pdf