Software interrupt in RISC-V port

bdawood wrote on Monday, July 08, 2019:


We are currently using FreeRTOS for our RISC-V development. One particular case I came across is that FreeRTOS trap_handlder doens’t handle at Software interrupts. So as far as I can understand, it checks if the source of the trap is async (i.e external IRQ or timer IRQ) or sync (probably due to illegal access). However In our code we rely on issuing a software interrupt to the core to do some stuff. So what happens is that FreeRTOS check its an async interrupt but yet not an external interrupt and goes and raise an assert (i.e ebreak instruction!!).

Is that actually the intended behavior? Am i missing something in here? Is there a workaround for this?



rtel wrote on Monday, July 08, 2019:

Duplicate of