Hi FreeRTOS board!
I’m trying to understand in details how FreeRTOS works internally to port it to a new architecture (details in a previous thread: https://sourceforge.net/projects/freertos/forums/forum/382005/topic/3738228).
On this architecture I have following possible exceptions/interruptions (simplified subset for readability):
- 8 IRQs (1 high-prio/non maskable and 7 prioritized)
- 1 software trap exception with higher priority than above mentioned IRQs
- 1 software trap exception with lower priority than above mentioned IRQs
I intended to implement portYield as a software trap exception/interrupt and use one of the 7 level-programmable IRQs for my timer/tick interrupt.
In a thread dedicated to ColdFire porting ( https://sourceforge.net/projects/freertos/forums/forum/382005/topic/3443802 ) I read that trap should not be used for yield since they are synchronous. I don’t really understand why this is a problem ?
Unfortunately I cannot manually generate “normal” interrupts (as with INT_FORCE on ColdFire) and only basically have the above mentioned mechanisms at disposal (2 traps and 8 IRQs). If I understand correctly both YIELD and interrupts must leave the stack in compatible states. I therefore do not really see how I can achieve this with my configuration mentioned above. Any hint? Does this sound similar to any other supported architecture which I could take as example ? I went through the different implementations and didn’t find any with a similar infrastructure, perhaps I missed one… What is the best approach to adopt in such a situation?
Thanks in advance for any hint/help in this matter !