kj-lin wrote on Thursday, October 17, 2019:
In FreeRTOS RISC-V trap handler (freertos_risc_v_trap_handler) function, it seems to switch to ISR stack without checking interrupt level, which will get problem if nested interrupt happens.
Does FreeRTOS RISC-V port support nested interrupt?
rtel wrote on Thursday, October 17, 2019:
At this time the port does not implement interrupt nesting, although the
port is under active development and we plan to add interrupt nesting at
a later date, especially where the code is executed on larger devices.
I am searching nested interrupt support for RISC-V and find this old post. I read the latest RISC-V port code, it looks not support nested interrupt so far (July 2022). If that is right, do you have a plan for implementing this feature ? I am learning RISC-V and hope I can help with this if needed.
Hello @HONGWANG! Thanks for reaching out. The previous update by Richard still stands. The port is active development and we plan on adding interrupt nesting in the future.
I am learning RISC-V and hope I can help with this if needed.
We welcome all help! The code is open source, so if you’re able to implement a feature you’d like to see please cut a pull request.