piero74 wrote on Thursday, November 24, 2011:
I do recall saying that even ARM’s own RTOS does not support it, but then I am only going on what I have been told, and I have not used it myself.
CORRECT! i found your post and i read it: MY MISTAKE, sorry!!
If you have a port that supports interrupt nesting, then I would definitely be interested and encourage you to post it to the FreeRTOS Interactive site
I tried something but i failed.
I have only a workaround, i modified a little the kernel to allow to my self to use SWI (reserved for RTSO tick) also for call functions inside SWI ISR, just using a macro that set a global variable (it is an index that allow to choose function) and call asm(SWI).
With this workaround, i’m using FIQ (even managing multiple sources in ISR) to nest IRQs, and i use the help of my custom SWI to allow that something in FIQ send a message to task (custom routine just use sendqueueInISR according with global variable)
SWI has low priority than IRQ, so message will be sent AFTER the end of current IRQ, so FIQ ISR could be a very fast routine with a very low latency, will have the ability to send (even postponed) a message to tasks, and IRQ routines nested will not delayed for a long time (send message from ISR waste time that could be too big for some IRQ with strict time constrains )
Let me know if could be useful to post this idea (i’m very busy at work too, so it will not be sooner)
Also, i have a contribution to implement above RTOS shared buffers, where many consumer tasks can use big data (buffers) from a producer task, forward pieces to other tasks, exchanging small info using queues, and without lock producer during buffer elaboration (i didn’t use semaphores)
Again, Let me know if could be useful to post this idea (i’m very busy at work too, so it will not be sooner: also i should document it very well)