Why RISCV port did not support taskENTER_CRITICAL_FROM_ISR

Kernel
1

I noticed the GCC RISCV port for taskENTER_CRITICAL_FROM_ISR() is:

#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue

why use this implementation for critical in ISR. I believe RISCV can support the nesting interupt, and this implementation can not work in ISR with nesting interrupt support.

2

You are right, interrupt nesting support is yet to be implemented.

3

Hi

I am curious about why nesting support has not be implemented because it is an important feature.

I noticed there is MINTTHRESH register in the CLIC like the basepri register in CotexM3, so it is easy to implement.

4

We updated the RISC-V port recently to support vectored and un-vectored interrupts, and will continue to add features, including nesting. As far as I’m aware the CLIC is not standard on all chips we test on, so it’s not as easy on some implementations.

5

Thanks for you detailed reply :wink: