anonymous wrote on Tuesday, November 08, 2011:
Hello,
I have a need to enable interrupt nesting in the SAM 7S port of Free RTOS.
From the code sample here:
http://gandalf.arubi.uni-kl.de/avr_projects/arm_projects/index_at91.html#at91uart_and_aic
it describes a technique in the ISR to store the registers to the IRQ stack, then enable interrupt nesting. At the end of the Interrupt routine, the registers are restored and interrupt nesting is disabled.
I am trying to figure out the proper way to integrate these macros into portISR.c (vPreemptiveTick function) and how to get them to work with the existing portSAVE_CONTEXT() / portRESTORE_CONTEXT() macros.
so far I’ve included the interrupt nesting macros outside portSAVE_CONTEXT() / portRESTORE_CONTEXT() - and inside- both crash the kernel. I’m starting to dig further now.
Any guidance would be great. After this is working I would be more than happy to contribute back interrupt nesting capability for the SAM7s port.
Thank you,
Brent Picasso
Macros from example that enable/disable interrupt nesting plus /save/restore
/******************************************************************************
*
* MACRO Name: ISR_STORE()
*
* Description:
* This MACRO is used upon entry to an ISR with interrupt nesting.
* Should be used together with ISR_ENABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
*
*****************************************************************************/
#define ISR_STORE() asm volatile( \
"STMDB SP!,{R0-R12,LR}\n" )
/******************************************************************************
*
* MACRO Name: ISR_RESTORE()
*
* Description:
* This MACRO is used upon exit from an ISR with interrupt nesting.
* Should be used together with ISR_DISABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
* 2 - Adjusts resume adress
*
*****************************************************************************/
#define ISR_RESTORE() asm volatile( \
"LDMIA SP!,{R0-R12,LR}\n" \
"SUBS R15,R14,#0x0004\n" )
/******************************************************************************
*
* MACRO Name: ISR_ENABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used after ISR_STORE.
*
*****************************************************************************/
#define ISR_ENABLE_NEST() asm volatile( \
"MRS LR, SPSR \n" \
"STMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x1F \n" \
"STMFD SP!, {LR} " )
/******************************************************************************
*
* MACRO Name: ISR_DISABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used before ISR_RESTORE.
*
*****************************************************************************/
#define ISR_DISABLE_NEST() asm volatile( \
"LDMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x92 \n" \
"LDMFD SP!, {LR} \n" \
"MSR SPSR_cxsf, LR \n" )