More than one IRQ interrupt source with TMS570 (LC43)

Kernel
1

simointe wrote on Monday, September 12, 2016:

(TMS570LC4, C++)
I have a fully functionnal FreeRtos implementation on TMS570.
My high frequency interrupt is on FIQ though, and now I want to change it on IRQ.
FreeRtos is on IRQ, are interrupts could be nested and how ?
I have already some assembler code to handle this in « usual C++ function » but I don’t know how to merge it within the vPortPreemptiveTick and vPortYeildWithinAPI interrupts.
You could refer to a previous post I’ve done.

https://sourceforge.net/p/freertos/discussion/382005/thread/0caeaa55/#45db

For others interrupt than FreeRtos, nesting seems to work (no crash at least) puting this 2 little codes before and after:

BEFORE
/// Copy SPSR_irq to LR
/// Save SPSR_irq
/// Enable IRQ and set System Mode
/// Save LR
//-----------------------------------------------------------------------------
{
asm( " ADD SP, SP, #8 " );
asm( " SUB LR, LR, #4 " );
asm( " SRSFD #0x12 ! " );
asm( " CPS #0x13 " );
asm( " PUSH {R0-R12} " );
asm( " FMRX R5,FPEXC " );
asm( " PUSH {R5} " );
asm( " FMRX R5,FPSCR " );
asm( " PUSH {R5} " );
asm( " FSTMDBD SP!, {D0-D7} " );
asm( " MOV R1, SP " );
asm( " AND R1, R1, #4 " );
asm( " SUB SP, SP, R1 " );
asm( " PUSH {R1, R14} " ); \

AFTER
/// Restore LR
/// Disable IRQ (IRQ Mode)
/// Restore SPSR_irq to LR
/// Copy LR to SPSR_irq
//-----------------------------------------------------------------------------
asm( " POP {R1, LR} " );
asm( " ADD SP, SP, r1 " );
asm( " FLDMIAD SP!, {D0-D7} " );
asm( " POP {R5} " );
asm( " FMXR FPSCR, R5 " );
asm( " POP {R5} " );
asm( " FMXR FPEXC, R5 " );
asm( " POP {R0-R12} " );
asm( " CPS #0x12 " );
asm( " RFEFD SP! " ); \

2

davedoors wrote on Tuesday, September 13, 2016:

It is normal to have more than one interrupt on the irq. Find some Cortex R irq nesting code here:

https://sourceforge.net/p/freertos/code/HEAD/tree/trunk/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S

or maybe here depending on your interrupt controller

https://sourceforge.net/p/freertos/code/HEAD/tree/trunk/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S

3

simointe wrote on Tuesday, September 13, 2016:

As you know, there is already a portAsm file in my ARM_Cortex-R4 directory.
This new file is to add, or merge ? Could-you indicate how to use it.
Thanks.

4

rtel wrote on Tuesday, September 13, 2016:

The link was to a generic Cortex-R port which supports interrupt
nesting. For historical reasons the RM48/TMS570 port is different, so
the files are not compatible.

See the “interrupt service routines” section of the following page for
information on adding additional interrupts
http://www.freertos.org/Free_RTOS_for_TI_RM48_and_TMS570.html

Search for all occurrences of vSCIInterruptHandler in the following file
to see how an interrupt is defined and installed.

https://sourceforge.net/p/freertos/code/HEAD/tree/trunk/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/serial.c

5

simointe wrote on Tuesday, September 13, 2016:

6

simointe wrote on Tuesday, September 20, 2016:

Thank you. The ISR section of the TMS570LC4 FreeRtos port indicates that there is no special thing to do comparing to compiler specifications.
Basically, it is said in the TMS that you just have to activate the interruption in the ISR if you want to be preampted by other high priority interrupt. The ISR that preampt have to take care of the context.
Now, I need some help to know where to enable the interrupt. I’ve tried many things no success.

vPortPreemptiveTick:

	; Save the context of the current task.
    portSAVE_CONTEXT

    ; Clear interrupt flag
    MOVW    R0, #0xFC88
    MOVT    R0, #0xFFFF
    MOV     R1, #1
    STR     R1, [R0]

    ;HERE ????????
    ;Enable int.
    CPSIE I

    ; Increment the tick count, making any adjustments to the blocked lists
    ; that may be necessary.
    BL      xTaskIncrementTick

    ; Select the next task to execute.
    CMP	R0, #0
    BLNE    vTaskSwitchContext

    ; Restore the context of the task selected to execute.
    portRESTORE_CONTEXT

Best Regards.