Using interrupts in a Cyclone V SoC, Cortex-A9 RTOS demo

heinbali01 wrote on Monday, October 16, 2017:

Has any one worked with the Altera Cyclone V SoC RTOS Demo ?

I’m writing a +TCP driver for the Cyclone V SoC. I want to use the HPS with Cortex-A9 and its peripherals, and I’m using mentioned demo as a start.

The EMAC and UART work fine, both transmission and reception, except that I never see any RX- or TX-interrupt occurring.

I am following these steps:

        vRegisterIRQHandler( ALT_INT_INTERRUPT_EMAC1_IRQ, vEMACIntHandler, ( void *)&xEMACif );
        alt_int_dist_priority_set( ALT_INT_INTERRUPT_EMAC1_IRQ, EMAC_INT_PRIOITY );
        alt_int_dist_enable( ALT_INT_INTERRUPT_EMAC1_IRQ );

		alt_int_dist_enable( ALT_INT_INTERRUPT_UART0 );
		vRegisterIRQHandler( ALT_INT_INTERRUPT_UART0, vUARTIntHandler, ( void *)pxUARTHandle );
		alt_int_dist_priority_set( ALT_INT_INTERRUPT_UART0, UART_INT_PRIOITY );

and I also set the peripheral’s IER (Interrupt Enable) bits for TX, RX and other events.

But the generic interrupt dispatcher, vApplicationIRQHandler() is only ever called for the FreeRTOS clock-tick, interrupt nr 29.

Is there a step that I missed somewhere?

thomask wrote on Tuesday, October 17, 2017:

Hi!

I will be using a Cyclone V SoC myself for an upcoming project, and would
be very interested in your driver!

Will it be released officially?

I already got the source code for a lwIP SoC EMAC driver from

http://code-time.com/bsp.html

(it’s BSD licensed!) and planned to port it to FreeRTOS. I could also send
you the code if you think it might help.

best regards,
thomas

On Mon, October 16, 2017 09:45, Hein Tibosch wrote:

Has any one worked with the Altera Cyclone V SoC RTOS
Demo
?

I’m writing a +TCP driver for the Cyclone V SoC. I want to use the HPS
with Cortex-A9 and its peripherals, and I’m using mentioned demo as a
start.

The EMAC and UART work fine, both transmission and reception, except that
I never see any RX- or TX-interrupt occurring.

I am following these steps:

vRegisterIRQHandler( ALT_INT_INTERRUPT_EMAC1_IRQ, vEMACIntHandler, ( void
*)&xEMACif );
alt_int_dist_priority_set( ALT_INT_INTERRUPT_EMAC1_IRQ, EMAC_INT_PRIOITY
);
alt_int_dist_enable( ALT_INT_INTERRUPT_EMAC1_IRQ );

alt_int_dist_enable( ALT_INT_INTERRUPT_UART0 ); vRegisterIRQHandler(
ALT_INT_INTERRUPT_UART0, vUARTIntHandler, ( void *)pxUARTHandle );
alt_int_dist_priority_set( ALT_INT_INTERRUPT_UART0, UART_INT_PRIOITY ); ```


and I also set the peripheral's IER (Interrupt Enable) bits for TX, RX
and other events.

But the generic interrupt dispatcher, `vApplicationIRQHandler()` is only
ever called for the FreeRTOS clock-tick, interrupt nr 29.

Is there a step that I missed somewhere?

heinbali01 wrote on Friday, November 03, 2017:

Thanks Thomas. In a meanwhile, we contacted each other by email.

The driver as published by Code-Time does set the EMAC interrupt, but the ISR seems to be empty.

As I was advised to ask this question directly on the Altera forum, I would like to move this thread to :

http://www.alteraforum.com/forum/showthread.php?t=56920&p=231485#post231485

Any findings will be published there. Thanks, Hein

heinbali01 wrote on Tuesday, November 07, 2017:

The problem is solved.

I had to call:

alt_int_dist_target_set( ALT_INT_INTERRUPT_EMAC1_IRQ, (alt_int_cpu_target_t) 0x01);

in order to direct the EMAC1 interrupts to the first core.

That call will set “Interrupt Processor Targets Registers”, which start at address 0x800 of the GIC

rtel wrote on Tuesday, November 07, 2017:

Thanks for reporting back so other can see.