Hey there !
In the context of my internship, I had a mid-term review during which I compared AMP and SMP Configuration. I told about the SMP Configuration requirements, and I had to explain the reasons behind.
There was no issue to explain why the cores should share the same memory, why they should have the same arm design. However, in a former topic I launched, I read :
Many Dual-Processors are set up with a High-Efficiency processor for lowest power operation, with a second High-performance processor that is put to sleep when not needed, but can be woken up when needed. This makes the processors asymmetrical […]
I went too fast in some conclusions, and I extrapolated : “The cores must be strictly identical : same frequency, same power supply, same efficiency and performances, same amount of cache…” My tutors threw me a curveball when They asked me “why”. I tried to answer, but I wasn’t convinced myself. I get asked to check again what I affirmed. Here is what I said :
-
Same Frequency :
I think that equal frequencies are required to have tick IT happening at the same time on each core. But my tutors opposed to me that the ISR triggering this IT, i.e.vPortYieldFromTick(), can’t run on both core at the same time ! Of course ! And it’s confirmed by this topic that the tick timer is only started on primary core. And after good sleep I remembered that same frequency do not imply they are in phase.
I think my problem is that misunderstand if the frequency depends on the ST/NXP design, or on the ARM archtecture . Now that I take a closer look to some technical specifications in arm developer datasheets, I see that they don’t precise a frequency, so it’s a part of funder designs. Thus, was my assumption of “identical frequencies” wrong ? -
Same power supply :
The idea was just that frequency depends on power. -
Same efficiency and performance :
When I read the previous quote, I thought that if two cores are not optimized for same performance and efficiency, a task rescheduled from one core to another will not run in the same condition, and it impact the real time. -
same amount of cache - the biggest piece :
I said that, when the scheduler reschedule a task on another core, if this core have less available cache, all the cached data can’t be copied and “there is an issue”. My tutor answered it’s a wrong reason, as FreeRTOS doesn’t handle how the cache is used.
Indeed, I looked atvPortYieldFromTick()and one of the implementations ofportSAVE_CONTEXT(): It doesn’t act on cache, only on core registers ! So there is no need to have the same amount of cache, is there ?
Now, I’m figuring out that… when a task is rescheduled from one core to another, the cached data can be lost without a hardware cache coherency solution. Some precautions would be needed, as explained here.
I’m glad I get “traped” on these questions now and not during the final examination. 
can you tell me if the “requirements” I listed (I thought of them by myself, I didn’t read them black on white in docs) are true ? If they are, what are the correct motivations behind them ? I suppose I should have read more carefully the 2040 example.
I understand that my questions can be a little bit basic. They are also precise, it’s because my internship subject requires a precise understanding, and I also want to level up myself on the topic, so please feel free to highlight my mistakes.
Thanks for reading. 