Initial comparison between SMP and AMP configurations

Hey there ! thanks for answers !

If the processor have private esRAM, then you need to give that up to work as SMP.

(sorry don’t know how to cite with names ? )

Well that’s my “hardware requirements” point : eNVM and esRAM are not private. But I’ve some concerns about cache and TCM. From what I see, cache and TCM are not inside the cores, but between the 2, within a “TCM matrix” and “cache matrix”. According to the intern datasheet, these matrixes can be splited at 70/30 or 100/0 (depending on configurations.) Here, I don’t understand well if even these memories have to be symmetric. I think it’s necessary, for example if a task (with no affinity setting) is moved from core 0 to core 1 by scheduler, with less available cache… Moreover, I don’t know if these matrix splits are imposed by hardware or software. In the first case, We’ll give up on SMP, of course. But other points are important : If they are all in sense of SMP, my tutor’s team do not exclude to modify hardware for next iterations, so I’m gathering the informations ! :slight_smile:

Another thing to consider is isolation - AMP provides you better isolation as those are 2 separate instances of FreeRTOS.

Thanks, another trail to follow ! :slight_smile: may it could be important for the safety component of the project.

We do not have an SMP port for Cortex-M7 but you can certainly write one (and upstream too :wink: ).

I’d like to ! as free software is important for me. But it will depend on the company : I can’t share what I want without the approval of my tutor. I guess it’s normal in international companies. :slight_smile: If they choose to use AMP, then it could be a great exercice to make the port on my free time. In that case there will be any issue if I share it.