SMP Porting to Cortex R5

Yes. the master core takes the tick and issues a soft interrupt to the remaining cores. The XMOS port is a good example of going beyond 2 cores.

Any I-Cache will be fine. D-Cache could be used but you will need to take special care.

  1. Lock the affinity of tasks that will use the data cache so they stay on a single CPU.
  2. Ensure that cached data is not shared between tasks that are not affined to a single CPU.

If the cache was flushed on every context switch you could use the cache in a single core system, but because the context switches can happen asynchronously tasks that share data can easily run into issues with the cache.

For the interested observers the ARM technical documentation is here: Documentation – Arm Developer