Setting up shared memory between two cores

1/ I have ordered the Discovery kit with STM32H745XI MCU. I do not have it yet.

2/ I am looking at the CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR example and can follow the instructions and have built both executables.

3/ I would like to define an unmanaged COMMON block that’s shared between the two processes, core 1 writes it, core 2 reads it; and I will use the message queue to send the ready flag.

Q1: In MessageBufferLocations.h I see the static declaration of the message buffers at #pragma location 0x380000200, so my first instinct would be to compute the offset of my shared memory and set it up as a static uint8_t big_buffer[1024]. Does this seem reasonable?

Q2: I have read thru other questions, so I’ve learned I should do a cache flush on the writer, but other than that is it as simple as this?

Q3: Is it in the HAL that the memory map is defined such that memory allocations “know” to avoid reserved blocks in the SDRAM?

Q4: I’m a 10+ year VxWorks user, so I’m used to a different way of doing things. So bear with me.

Thanks to anyone who helps!!

(Again, no hardware til Thursday, but I’m trying to understand)

You will need to edit the linker script so the block you want to share between the cores is not known to either core - that way the linker won’t use it for anything and you can have free access to it. As to whether that is done in the HAL or not - if the linker script is in the HAL then the answer would be yes, but I’m not sure where the linker script is. Sometimes IAR projects use a single central linker script for the device as the device is known to IAR - however in that project the linker script has already been messed with to place the message buffers in memory so I assume the linker script is already part of the project.

Thank you.
I am pouring over the project files; and there are a LOT of files!
I may be tackling to much… multi-core MPU, new RTOS, new IDE…