RISC-V tick setup wrong?

Kernel
1

Hi,

Currently the RISV port of FreeRTOS configures the timer increment per tick in port.c as this:

const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won’t go over 32-bits. */

But the tick is not taken directly from the CPU clock frequency. Would it be better to rename configCPU_CLOCK_HZ to configTICK_CLOCK_HZ to prevent any ambiguity. I couldn’t see configCPU_CLOCK_HZ being used for anything else in the RISCV port.

On a general note the RISV documentation is quite out of date particularly around interrupts.

Thanks

Nigel

2

Thank you for pointing this out. The following is form the RISC-V spec:

Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, mtime. mtime must increment at constant frequency, and the platform must provide a mechanism for determining the period of an mtime tick.

As the mtime frequency does not have to be same as CPU frequency, this proposal sounds good to me. Would you be willing to raise a PR?

I assume you are talking about support for vectored interrupts. If yes, I agree that needs to be updated. We always welcome contributions :slight_smile:

1 Like