rtel wrote on Monday, December 31, 2012:
All the (non exception) interrupt priorities can be configured directly by writing to the NVIC (Nested Vectored Interrupt Controller) registers, which are part of the Cortex-M3 core. Working out how to do this directly is however somewhat difficult and required reading the Cortex-M technical reference manuals from ARM (to get the register addresses) and the datasheet from the microcontroller manufacturer (to find which peripheral interrupts map to which NVIC interrupts). Therefore, these days at least, it is extremely rare to try and do this yourself. Instead there are library functions that make the task much easier.
If you are using CMSIS libraries then you can use the NVIC_SetPriority() function. For example on the LPC17xx you can call NVIC_SetPriority(TIMER0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY); to give an interrupt priority the maximum value allowable if it uses a FreeRTOS API function .
Other manufacturers use different API functions, but the CMSIS version is normally available too.
There are two things that complicate it further (interrupts on the Cortex-M are generally more complex than other CPUs):
1) Different microcontrollers implement a different number priority bits. Again if you are using CMSIS you should have __NVIC_PRIO_BITS defined which tells you how many there are. On the LPC17xx I think it is 4, so priorities can go from 0 (the highest) to 0x0f (the lowest).
2) The priority bits are sub-divided into preemption priority and sub priority. You want all the bits to be assigned to be preemption priority bits, and that is the default in the NXP libraries so you need not worry about that (generally in my experience the libraries from ST are the only ones where this is not the case.
Further reading on the subject if you are feeling brave: