I don’t know how this community works, so i am just telling what i need to ask.
so i am working on a custom risc_v core, its a 5 stage piped one, this will be running on an bysis3 board, i want rtos to be working on this core, can someone guide me through this?
As part of modifications that you are making to your custom RISC-V core, are you introducing any additional registers (beyond the standard RISC-V register set) that need to be saved and restored as part of the task context? If yes, you should be able to leverage the chip_specific_extensions mechanism in the FreeRTOS RISC-V port which allows you to define macros that store and restore any additional, non-standard registers during a context switch, without needing to modify the core port code.