Hi.
I am starting a project based on a Mini-Module Plus board and I want to use the new TCP stack (not LwIP).
The SDK from Xilinx provides older FreeRTOS versions and LwIP Stack demo.
On the other side, FreeRTOS has a demo on MicroZed or ZC702 boards, but not on Mini-Module Plus.
I have been investigating how to port to Mini-Module Plus, but it is not easy, as I don’t know even how to configure the Ethernet periperal in Vivado (DMA? FIFO?) to generate the corresponding bitstream.
Maybe the Ethernet and the rest of the peripherals of the demo does not need any bitstream to run?
Any information will be welcome on how to generate a Mini-Module Plus Hw platform to add to the other Hw platforms (MicroZed & ZC72)
By the way, I have tryed to follow the guide as if I had a MicroZed board, but it does not compile because does not find the RTOSDemo_bsp Which is already in the workspace.
Is there any plan to port Freertos to Mini-Module Plus?
I think that it should be very simple for the people that ported it to MicroZed & ZC72, as the hardware is very similar.
The FreeRTOS+TCP code running on the Zynq does not use any hardware
outside of the hard wired Cortex-A9 itself (including the hard wired
peripherals such as the Ethernet MAC). So there should not really be
any porting required, and a hardware specific FPGA image is not required
in fact as far as I know an FPGA image is not required at all. The
only things to take note of are:
The PHY in use - if the code does not run then the first thing to
look at is whether the PHY on your board is the same as that used on the
other supported platforms. Maybe a few small changes are needed there.
The memory layout of the board - perhaps the linker script and heap
initialisation needs changing for a different memory map.
The ports used for LED outputs - but LED outputs are only used for
convenience (to show something is running) so are not necessary for the
demo to actually run.
Previous Labs releases have required the BSP project to be generated by
the user. The latest releases are packaged differently, and now
actually include the BSP, so you don’t need to generate it any more.
As nothing outside of the Cortex-A9 is used you can probably use the BSP
exactly as it is shipped in the FreeRTOS Labs download - at least in the
first instance. So I would recommend taking the latest labs release
(from yesterday, as it happens), importing all three projects (hardware
project, BSP project, and application project) into the 2016.2 version
of the XSDK, and check that it builds as the first step.
The problem is that I need to use my own BSP project, as I will need to use the FPGA for some other functions ine the project.
I have tryed to do a BSP in Vivado to replace the BSP of the example with my own, but when I add the Ethernet IP (of the ARM processor block), there are configurations tah I don’t know how to set. For instance there is a selection of using DMA or FIFO for data transfer.
In fact, instead of porting the FreeRTOS, it could be more useful to have some kind of tutorial showing all the steps to follow in Vivado for generating a BSP.
As I understand, it is not really a software porting what I need, as I am almost sure that the Sw is the same for both modules, but only a BSP generation process.
If you can give me some info about the key points that sould be taken in account for the BSP generation I will try to get it working.
The problem is that I need to use my own BSP project, as I will need
to use the FPGA for some other functions ine the project. I have
tryed to do a BSP in Vivado to replace the BSP of the example with my
own, but when I add the Ethernet IP (of the ARM processor block),
As I understand it, you do not need to add Ethernet IP yourself, unless
you are going to use an Ethernet controller other than the one that is
already hard wired in the Cortex-A processor on the Zynq.
there are configurations tah I don’t know how to set. For instance
there is a selection of using DMA or FIFO for data transfer.
I’m afraid these fall far outside what is considered FreeRTOS support.
In fact, instead of porting the FreeRTOS, it could be more useful to
have some kind of tutorial showing all the steps to follow in Vivado
for generating a BSP.
As above, that is really a Xilinx support question, not a FreeRTOS
support issue.