Dual-Core Inter Processor Interrupts on Zynq Ultrascale MPSoC

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Hello, I am trying to set up interrupts between 2 cores on the Cortex A53. I am able to successfully fire an IPI from core 1 to core 0 but I can not figure out my issue when trying to fire an interrupt from core 0 to core 1 as well. Here is my initialization code for each core. I am wondering if it has something to do with initializing the GIC on both cores. I am not sure so please share your thoughts.

Below is the interrupt configuration code I wrote for both cores. This is my code for setting up both cores to fire and receive an IPI. (this does not work, but when I remove the GIC initialize code on core 0 I am able to fire and receive an IPI on core 1 only)

Core 0:
// Initialize the IPI instance and enable interrupts

ConfigPtr0 = XIpiPsu_LookupConfig(XPAR_XIPIPSU_0_DEVICE_ID);

XIpiPsu_CfgInitialize(&IpiInst0, ConfigPtr0, ConfigPtr0->BaseAddress);



// Initialize the GIC instance

IntcConfig0 = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);

XScuGic_CfgInitialize(&GicInst0, IntcConfig0, IntcConfig0->CpuBaseAddress);



// Initialize the GIC interrupt handler

Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,

    (Xil_ExceptionHandler) XScuGic_InterruptHandler, &GicInst0);



// Initialize the IPI interrupt handler

XScuGic_Connect(&GicInst0, IpiInst0.Config.IntId,

    (Xil_InterruptHandler) InterruptServiceRoutine0, (void \*) &IpiInst0);



XScuGic_Enable(&GicInst0, IpiInst0.Config.IntId);



XIpiPsu_ClearInterruptStatus(&IpiInst0, TARGET_CPU0_MASK);

XIpiPsu_InterruptEnable(&IpiInst0, TARGET_CPU0_MASK);



/\* Enable interrupts \*/

Xil_ExceptionEnable();

Core 1:
// Initialize the IPI instance and enable interrupts CORE0–>CORE1

ConfigPtr1 = XIpiPsu_LookupConfig(XPAR_XIPIPSU_0_DEVICE_ID);

XIpiPsu_CfgInitialize(&IpiInst1, ConfigPtr1, ConfigPtr1->BaseAddress);



// Initialize the GIC instance

IntcConfig1 = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);

XScuGic_CfgInitialize(&GicInst1, IntcConfig1, IntcConfig1->CpuBaseAddress);



// Initialize the GIC interrupt handler

Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,

    (Xil_ExceptionHandler) XScuGic_InterruptHandler, &GicInst1);



// Initialize the IPI interrupt handler

XScuGic_Connect(&GicInst1, IpiInst1.Config.IntId,

    (Xil_InterruptHandler) InterruptServiceRoutine, (void \*) &IpiInst1);



XScuGic_Enable(&GicInst1, IpiInst1.Config.IntId);



XIpiPsu_ClearInterruptStatus(&IpiInst1, TARGET_CPU1_MASK);

XIpiPsu_InterruptEnable(&IpiInst1, TARGET_CPU1_MASK);



/\* Enable interrupts \*/

Xil_ExceptionEnable();
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Your question is very specific to Xilinx hardware. I’d recommend reaching out to Xilinx for better support.