ZYNQ maskable IRQ

Kernel
1

sterossi84 wrote on Thursday, November 22, 2018:

Hi guys,

I’m using a dual-core ZYNQ device running in AMP fashion. Both cores run Cortex-A9 FreeRTOS port.
Each core owns a set of peripheral and manages the related interrupts.
For the sake of discussion let’s say that Core0 fully owns PS UART0 and CAN0 while Core1 fully owns PS CAN1.

As far as I’ve understood the logic that enables/disables single IRQ source is implemented in GIC distributor that is a shared resource.
In particular GIC distributor ISERn and ICERn registers can be used for the en/dis purpose.

I would like to implement critical sections that targets single interrupt source instead of whole core interrupts.
In this way I can temporary disable UART0 IRQ leaving CAN0 IRQ unaffected for example.

In a single core context I would normally use ISERn and ICERn registers.
In the current case instead the ISERn and ICERn are shared and can be accessed by both ZYNQ cores. That’s why arbitration issue arises.

Given that each core will operate on the owned IRQs, what happens if both cores try to write to the same register at the same time? How arbitration is managed?
Is there any other way to mask single interrupt source without affecting the other ones?

Thanks in advance

2

richarddamon wrote on Thursday, November 22, 2018:

One of the reasons for having Set and Clear registers rather than doing a read-modify-write to an enable register is that the Set and Clear operations are atomic, so if the two cores try to adjust the mask register at the same time, and it is not that one processor is setting a given flag while the other is reseting that SAME flag, things should just work. If you try contradictory operations on a bit the which one actually happens second will dominate.