Cortex M4 hard fault finding root cause on LPC4078

[carlk3 (Carl Kugler III)]

@richard-damon

Now, what would really be better is if more processors had a stack limit register that generated a trap if the stack pointer passed the limit…

I agree. +1 for Cortex-M33.

@aggarg

@carlk3

For processors based on the Armv8-M Mainline architecture, each of the stack pointers has a corresponding stack limit register which allows software to define watermark levels for stack overflow detection, and when stack overflow occurs, a Usage fault or HardFault exception is triggered.

FreeRTOS Cortex-M33 ports do program the stack limit register for each task - as a result, any stack overflow triggers a Usage fault or HardFault exception.