Deferred Interrupt Processing and posting a Binary Semaphore more than once

I guess what I am grasping for is something like the new stack limit checking features in the Armv8-M architecture: For processors based on the Armv8-M Mainline architecture, each of the stack pointers has a corresponding stack limit register which allows software to define watermark levels for stack overflow detection, and when stack overflow occurs, a Usage fault or HardFault exception is triggered.