I am attempting to use FreeRTOS on the Zynq platform to build an application that uses AXI Dma to transfer data from the Zynq fabric to the Zynq processor. Then process the data and use TCP to transfer the processed data to the real world. Just to be clear I am new to the FreeRTOS environment.
I made the following steps to get to where I am now to be sure I understand each step.
- Made an application that would get Dma interrupts from data generated in the Zynq fabric. The application did not use FreeRTOS, it was just a bare metal application that got the interrupts and looked at the data to be sure I got the correct amount and correct values.
- Made an application that implemented the blinky demo and used the FreeRTOS labs UDP demo to write messages. From this I know I can write messages to the UDP terminal from a basic Zynq application. No great accomplishment.
- I then made several attempts to merge the DMA application into the UDP/Blinky application and I seem to be unable to get the DMA interrupt to fire. In the DMA Handler I simply write to the UDP server that the interrupt was processed. The Zynq hardware is setup to generate one single interrupt, thats what it does in the first application, but I can’t seem get it to fire in the combined version. I can post the combined hardware setup if it might help.
The difference between the UDP/Blinky application and the UDP/Blinky/DMA is that the DMA requires memory to be reserved and I can’t yet see where FreeRTOS allows for the block of memory to be blocked .
I have two devices in the Zynq fabric and maybe this is causing my problem, I suspect not but just want to be understand better. Is there a way to mask these segments from FreeRTOS?
#define XPAR_CCMAXIREGISTER_0_DEVICE_ID 0 #define XPAR_CCMAXIREGISTER_0_S00_AXI_BASEADDR 0x43C00000 #define XPAR_CCMAXIREGISTER_0_S00_AXI_HIGHADDR 0x43C0FFFF #define XPAR_AXI_DMA_0_DEVICE_ID 0 #define XPAR_AXI_DMA_0_BASEADDR 0x40400000 #define XPAR_AXI_DMA_0_HIGHADDR 0x4040FFFF