I am trying to get the demo for the Nios ii running on my own board design. I am using a cyclone III similar to the one on the reference board used for the demo project. Having said that, it is a different card and the FPGA design is unique along with the Nios I have other custom logic blocks. In theory if I can setup the Nios (sopc design) with the same resources as the demo boards FPGA design things should work fine or if I knew how to specify the hardware resources the FreeRTOS code uses I could make my sopc design work as well.
The .ptf file is the only included hardware file for the FPGA design rather than the .sopc file which you could open up and view to see what hardware resources are required to run the demo or exactly what the demo fpga design has.
I have been able to create the Nios IDE project and point to my sopc design and when I compile I am getting an error with some of the code associated with the timer Interrupt which I am sure is because the code is trying to use a timer block inside sopc design that does not exists in my design that was there in the demo fpga design.
Does anyone know how or where the code and hardware peripherals get “tied” together ?