Using Nios demo project on custom FPGA design

dsmhmm wrote on Wednesday, May 05, 2010:

I am trying to get the demo for the Nios ii running on my own board design.  I am using a cyclone III similar to the one on the reference board used for the demo project.  Having said that, it is a different card and the FPGA design is unique along with the Nios I have other custom logic blocks.  In theory if I can setup the Nios (sopc design) with the same resources as the demo boards FPGA design things should work fine or if I knew how to specify the hardware resources the FreeRTOS code uses I could make my sopc design work as well.

The .ptf file is the only included hardware file for the FPGA design rather than the .sopc file which you could open up and view to see what hardware resources are required to run the demo or exactly what the demo fpga design has.

I have been able to create the Nios IDE project and point to my sopc design and when I compile I am getting an error with some of the code associated with the timer Interrupt which I am sure is because the code is trying to use a timer block inside sopc design that does not exists in my design that was there in the demo fpga design.

Does anyone know how or where the code and hardware peripherals get “tied” together ?  

rtel wrote on Monday, May 10, 2010:

I asked William about this (William is the NIOS man), and this is his response:

I think that the root of the problem is that the latest Altera tools have changed the way the system library is created. The ‘syslib’ project is now called ‘BSP’ and requires a different file to generate the necessary hardware description for the software. Therefore, I think that the ‘ptf’ has been deprecated, or at the very least, it cannot be used by the Nios environment.

When I tried to use the latest Altera software, I came across this problem but rolled back the Altera software because I didn’t have the FPGA project to generate the necessary files. In theory, you could use the latest Quartus to create the files because you have the FPGA design for the EBV DBC3C40 board.

More appropriately for ‘dsmhmm’, he just needs to do a find and replace of ‘SYS_CLK_’ to the name of his Timer peripheral in port.c. Replacing ‘SYS_CLK_’ will catch ‘SYS_CLK_BASE’, which is the memory mapped address of the peripheral, and ‘SYS_CLK_IRQ’, which is the IRQ number.

I am not 100% sure about the new format mainly because I haven’t tried it but at the very least ‘dsmhmm’ will know which lines need to be changed in the port layer code.