Seem to in demo config for STM32 CortexM3 arch is small bug (rather non consistency) but without side effects.
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */
According http://www.st.com/stonline/products/literature/pm/15491.pdf page 20,
in BASEPRI only bits 7:4 are valid. So I expect rather:
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (11U<<4U) /* equivalent to 0xb0, or priority 11. */
11U<<4U is 0xB0, what is also priority 11.
It is equivalent of 191 (0xBF), since from documentation bits 3:0 are reserved.