The Cortex M3 is designed with ‘forward compatibility’ in mind (sounds like their marketing dept. got involved in that). This is why the interrupt mechanism is so confusing. The Cortex M3 itself has 8 bits of priority, but different implementations use a different number of bits. In the interest of ‘forward compatibility’ it is the most significant bits that are actually used, the idea being that code will be portable to future revisions of the cpu that might implement more bits.
The way the code is written is deliberate, and fine as it is. A lot of this code was written before the CMSIS stuff existed, and before most of the documentation on the CM3 was publicly available.