Hi.
Just tested out 7.0.0 (from 6.1.1, transition works great!) and had a quick look at the new STM32F100 demo. In its brand-new FreeRTOSConfig.h, there is
/* Priority 5, or 160 as only the top three bits are implemented. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
Seems that someone finally stumbled over those neat inversed priorities
As lowest priority 15 equals 240 (top three bits), I think there should be written either priority 5 aka 80 (top three bits), or priority 10 aka 160 (top three bits). Don’t know which one was intended now.
Hm, now I am more confused. What does “top three bits”, which I also stupidly copied from the header file, mean? For priorities in 0…15 (high…low), there are 4 bits needed. Am I completely wrong now?
Felix
Opps. Cut and paste is the route of all evil. Some CM3 chips only implement three bits of priority.
The code itself is I think correct, but the comment incorrect.
The top *four* bits are implemented, so priority 5 in binary is 01011111, with the low (unimplemented) four bits set to 1 for future compatibility (if the chip implements more bits in the future). 01011111 (binary) = 95 (decimal), therefore the comment should read:
“/* Priority 5, or 95 as only the top four bits are implemented. */”
do you agree with that? I have changed it in SVN already, so let me know if you don’t agree.
OK, thanks Richard. Though the “STM32F10xxx Cortex-M3 programming manual” (PM0056, p. 126) says that bits of a NVIC_IPRx byte always read zero, it’s indeed better for compatibility.
