SPI1 ISR help

hudson2009 wrote on Thursday, March 19, 2009:

Hi,

I am working AT91SAM7X FreeRTOS.
trying to get the SPI1 working as a slave with interrupt on RDRF.

However the ISR never happen, can any one help?
Following are initialization code:

//=================================
//  ARM7 SPI1               MSP430 SPIA
// -----------              ----------
//     PA21  |<- NCPS0 -  | P3.7
//     PA22  |<- SCLK -   | P3.0
//     PA23  |< - MOSI -  | P3.4
//     pa24  | - MISO ->  | P3.5
// -----------              ----------
//=================================
void vSPI1_Init(void)
{

  portENTER_CRITICAL();
  {
    // Config SPI1 PIO -
    AT91C_BASE_PIOA ->PIO_PDR = (AT91C_PA21_NPCS10| AT91C_PA24_MISO1 | AT91C_PA23_MOSI1 | AT91C_PA22_SPCK1);// Set in Periph mode
    AT91C_BASE_PIOA ->PIO_BSR = (AT91C_PA21_NPCS10| AT91C_PA24_MISO1 | AT91C_PA23_MOSI1 | AT91C_PA22_SPCK1);   
   
    // Config PMC
    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI1;

    //SPI software reset
    AT91C_BASE_SPI1->SPI_CR = AT91C_SPI_SWRST;

   // cfg MR 9slave mode)
    AT91C_BASE_SPI1->SPI_MR = AT91C_SPI_MODFDIS;

   // cfg CSR
    AT91C_BASE_SPI1->SPI_CSR[0] = (0 + 0 + AT91C_SPI_BITS_8);

    // Configure SPI interrupt
    // AT91F_AIC_ConfigureIt
    //----------------------------------------------------------------------------------------------------     
    AT91C_BASE_AIC->AIC_IDCR = 0x01<< AT91C_ID_SPI1;
    // Save the interrupt handler routine pointer and the interrupt priority
    AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SPI1] = (unsigned int)vSPI_ISR_Wrapper;
    // Store the Source Mode Register
    //AT91C_BASE_AIC-> AIC_SMR[AT91C_ID_SPI1]= AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ;
    // Clear the interrupt on the interrupt controller
    AT91C_BASE_AIC->AIC_ICCR = 0x01<< AT91C_ID_SPI1;
    //----------------------------------------------------------------------------------------------------  
    //AT91F_AIC_EnableIt
    AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SPI1;

    // Enable interrupt aacordingly
    AT91C_BASE_SPI1 -> SPI_IDR =  (AT91C_SPI_RDRF + AT91C_SPI_TDRE + AT91C_SPI_MODF + AT91C_SPI_OVRES+
                                   AT91C_SPI_NSSR + AT91C_SPI_TXEMPTY + AT91C_SPI_SPIENS);
    AT91C_BASE_SPI1 -> SPI_IER =  AT91C_SPI_RDRF;

    // Disable the PDC transfer   
    AT91C_BASE_SPI1->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;

   // SPI is enable
    AT91C_BASE_SPI1->SPI_CR = AT91C_SPI_SPIEN;

  }
  portEXIT_CRITICAL();
}

void vSPI1_ISR_Wrapper( void )__attribute__ ((naked));
void vSPI1_ISR_Handler( void );

void vSPI1_ISR_Wrapper( void )
{
    portSAVE_CONTEXT();
    vSPI_ISR_Handler();
    portRESTORE_CONTEXT();
}

/*-----------------------------------------------------------*/
void vSPI1_ISR_Handler( void )
{
     unsigned long spi_Status;   
     signed portCHAR RxChar;
      AT91PS_SPI     pSPI = AT91C_BASE_SPI1;
   
      spi_Status = (pSPI -> SPI_SR);
       
    // A data has been recieved and transmitted to the RBR.
    if (spi_Status & AT91C_SPI_RDRF)   
    {
        spi_Rdrf_Flag = 1;
    }
        /* End the interrupt in the AIC. */
        AT91C_BASE_AIC->AIC_EOICR = 0;
}
/*-----------------------------------------------------------*/

hudson2009 wrote on Thursday, March 19, 2009:

found the problem.

MASTER not driving the CS line LOW.

:stuck_out_tongue: