We make an attempt to port SMP version to Cortex R5. Work is inspired by RP2040 port.
I’d appreciate some porting checklist.
- Tick interrupt. Happens only on master core or identical on both (all cores)? Other scheme?
- Ignition and initialization of Second core. Simple loop that waits for sp, pc (xPortStartSchedulerOnCore or xPortStartScheduler) and interrupt table address , once set jumps to given pc. Is this correct?
- What else we need to know to implement multi-core safe mutexes, locks, etc. Is there some dependency of Processor SDK (out of FreeRTOS source tree)?
- Any static data that kernel uses that we need to be aware of?
- If I understand correctly, both cores run the same scheduler, and it picks tasks from queue that is visible on both cores. Is it correct?
Our target is offloading of computation tasks to the second core, no need in Interrupts/peripherals access on the second core.
Any help would be appreciated.