Hello, my name is André Zeps and I’m an engineer at Kostal Automotive in Germany.
I’m pretty new to the FreeRTOS forum but I thought it would make sense to make an account now.
I’m currently trying to port the SMP branch to an Infineon Traveo II which offers a dual core Cortex M7. Documentation about the porting process is pretty scarce but some threads in the forum here and also the source code of the rp2040 helped a lot.
SMP Porting Checklist - A53 *4 as reference seems to be an unofficial porting guide.
Sadly, not everyone had a satisfying result in the end though: SMP Porting to Cortex R5 - #29 by akj90
While it is pretty clear that spinlock hardware must exist to support mutual exclusion, this is not directly apparent for cache coherency which seems to be essential for fast performing SMP. Neither XCore AI nor RP2040 have any DCache so they don’t have any issue with that.
My current work is based on the deactivation of the DCache and I’m wondering how it could possibly be activated without any stochastic issues in the future.
The whole kernel must either be in a non-cache area or the cache must be frequently invalidated.
The heap data and the “heap organization structure” also has to be suitable for the task.
I wanted to create this thread here to discuss how much thought yet was invested into cache coherency for CPUs that are not supporting it with a snooping protocol. I would expect to have some sort of macro which the kernel could use to invalidate certain areas which could have been touched by the other core. This macro would then have to be implemented for every supported controller.
Or is my task already in vain and SMP is not something that should be done on a controller without cache synchronization hardware?