SMP port for AM234x

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Hi All,
I recently got a hold of a TMDS243EVM board from Texas Instruments and would love to try out the latest FreeRTOS SMP kernel on it.
Does an SMP port exist for the Sitara AM234x SoC or does anyone know if one is being developed.
I found the AM64x partner supported demo but nothing on the R5F-based AM234x

Thanks in advance

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Hey @epopov, hope you’re doing well

I’m not aware of if any port exists for that SOC. Does that dev kit require the use of the TI compiler? If so there are Code Composer Studio (CCS) compatible ports for the Cortex-M4F and R4. The R4 port should be compatible with the R5.

I believe that this older thread about SMP for the R5 and then the guide for FreeRTOS SMP would probably be good places to start.

If you end up creating a port for the Sitara AM234x SoC we’d greatly appreciate it if you up-streamed it to the FreeRTOS-Kernel repo :slight_smile:

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Thanks for your response @skptak
I just had to ask. Sometimes luck is on our side and it was worth checking if someone has already done the heavy lifting.

In my original search I found a different ( and much less useful ) thread about R5, so you pointing me to that “SMP for the R5” is much appreciated.

I’m still pretty new to this SoC and dev-board, but the demos for the AM234 EVM can be compiled with either gcc or TI’s compiler through CCS. Texas Instruments do have an R5F and M4F FreeRTOS port for their C compiler. Those ports are offered as part of their MCU+SDK so I don’t think I need to resort to using the R4 port.

I’m looking into the AM243 as a proof of concept for future development and sadly, it is not my main focus. Also, I feel a bit overwhelmed by the prospect of trying to creating an SMT port for an SoC and CPU that are completely new to me, so I doubt that I’ll be able to contribute much, but who knows. In my spare time, I will try to get familiar with TI’s R5 single core port and maybe dabble into some assembly with the SMP checklist in hand.

Again, thanks for the input.
I’ll keep my fingers crossed that someone from TI sees this thread and decides to update their portfolio of partner supported ports :wink:

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The port you are looking for is here:

It uses the A53’s Cores in SMP mode. The R5 cores are not part of the demo for two reasons.

  1. The R5’s are on separate memory spaces not shared with the A53’s. and
  2. FreeRTOS does not support a dissimilar cores in the scheduler.
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@jjulich

I think you are referring to a port that runs on the TMDS64EVM evaluation board which uses the AM6442 SoC. That SoC has dual A53, quad R5F, and a single M4F Those SoCs are referred to as AM64x on the TI’ website

I’m using the TMDS342EVM evaluation board. It uses the AM2434 SoC which has 2 dual R5F ( for a total of 4 R5F cores ) and a single M4F. Those SoCs are referred to as AM243x on TI’s website.
I’m trying to run SMP on the quad R5F cores.

I don’t think I can use the AM64x SMP port you are referring to on a AM243x device. Am I missing something? Did I misunderstand you maybe?

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Ah. I have not studied the board you are using. I hope the R5’s share the memory or you will be forced into AMP.

Joseph Julicher

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Here’s a post linked in the TI’s FAQ for the AM234x:
AM2x: FreeRTOS Multiprocessing?

I made a summary of what I’ve gathered from posts, the datasheet, and the TRM:

  • The R5FSS is a dual-core unit that can run as 2 individual or a single core. The AM2342 has two of these for a max total of 4 individual cores.
  • Section 6.2.3.2.1 of the TRM (technical reference manual) states that each core has it’s own dedicated 16KB I-Cache and 16KB D-Cache. None of this is shared across cores and this is the biggest roadblock for implementing SMP
  • Each core has it’s own dedicated 32KB + 16KB +16KB = 64KB of TCM that can be used for instructions or data. In single-core mode, this TCM simply doubles to 128KB. This is another big roadblock for SMP
  • It appears that the only shared memory is the the 2MB of SRAM that is present in the SoC.
  • I have not explored if the I-Cache and D-Cache can be disabled and SMP implemented only in SRAM, but in the post linked above, the TI engineers say that due to the lack of cache coherency, they “do not expect SMP implementation to yield reasonable performance across different use cases”.
  • Here’s a post on e2e.ti.com on disabling cache. The post is about the AM6442 but it gives a good starting point like using SysConfig for making memory regions non-cached or using their DPL API. Here’s a link to the API cache documentation for the AM243
  • If the SoC has DDR attached, I’d claim we can apply the same reasoning as in the SRAM case.

In conclusion, I agree with the TI engineers that if you can’t use cache, performance will suffer greatly, but still, 4 cores running at 800Mhz each and a 2MB of SRAM sound pretty interesting. I don’t know what the internal SRAM clock and throughput’s are but those would be the limiting factor for SMP performance if/when all cache is disabled.
Even though the AM243x SoC is not ideal for FreeRTOS SMP, it still sounds intriguing and worth a try. I doubt that I will have time to tackle this myself, but maybe this post saves the next guy some time by giving them some quick pointers.

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