rtel wrote on Wednesday, July 30, 2008:
This depends on the port you are using. Here are some examples:
1) Cortex M3
Cortex M3 ports allow interrupts above the kernel interrupt priority (this feature is extended even further in the next release) so these interrupts are never held up by the kernel activity at all. The demos applications run a high frequency timer interrupt at 20KHz then measure the jitter in the interrupts execution - which comes out between 80ns and 160ns depending on the frequency at which the CPU is running. This jitter is totally an effect of the interrupt tail chaining (a feature that allows you to short cut interrupt entry) and nothing to do with the kernel. I have not tried a 100KHz interrupt, but at any frequency if the interrupt is above the kernel priority then it will not get delayed by the kernel so its just a matter of whether or not the processor can operate that quickly.
Likewise on the PIC32 you can run interrupts above the kernel interrupt priority. Although the measured jitter is a little longer when defining normal interrupts you have the option of using the level 7 priority and therefore the shadow registers which should give you super fast and accurate interrupt entry as the context need not be saved.
On the ARM7 you can use the FIQ interrupt, but make sure that the critical section entry code only disables IRQ interrupts, not FIQ interrupts.
The best thing to do is buy an inexpensive eval board and give it a try.