Reviewer routing for RISC-V timer-path PR #1482

Kernel
1

Hi,

I submitted a focused optimization for the generic GCC RISC-V machine-timer path:

Issue: [Feature Request] Defer RISC-V callee-saved register handling on no-switch timer interrupts · Issue #1464 · FreeRTOS/FreeRTOS-Kernel · GitHub
PR: Defer RISC-V callee-saved registers on no-switch timer interrupts by zhouzhou-code · Pull Request #1482 · FreeRTOS/FreeRTOS-Kernel · GitHub

It defers saving s0-s11 when xTaskIncrementTick() returns pdFALSE. The change has been validated on QEMU and JH7110 hardware, and
the PR checks pass.

Could someone help route this to the appropriate RISC-V port reviewer? I am happy to rebase or adjust the implementation.

Thanks.

2

Thank you for raising the PR. I will take a look.