Renesas RZ Linker file and binary

qwedvit wrote on Tuesday, November 18, 2014:


I’ve managed to get the FreeRTOS version for the RZ processor compile succesfully. According to the documentation this (unofficial) sample is written for the Renesas RSK. However, I’m using my own prototype platform. The target platform is comparable to the RSK in the sense that it uses the exact same QSPI flash (though single channel), but it does not include the external SDRAM.
On which address do I need to flash the FreeRTOS in order to get it running? I’m assuming that the statically linked properties of the FreeRTOS mean that a bootloader is included?

Also if I want to use the bootloader from the Renesas sample programs (single channel QSPI) the bootloader looks at address 0x18080000 in the QSPI for a valid user application. It uses offset 0x2C. Offset 0x20 contains the start address of the code, offset 0x24 contains the end address, and 0x28 conatains the execution start address. For the sample TFT project from Renesas this results in: starting address 0x20040000, end address 0x2009D3D0 and execution start address 0x20040000. Which in fact tells me that the program is copied into RAM, page 4 for execution. However if I look at the binary code of the sample FreeRTOS for this processor, it shows me starting address 0x20F00000 if I’m correct. This starting address goes way beyond the on chip RAM address of 0x209FFFFF. Do I need to modify this address in the code? And if so, where is it configured?

Thanks in advance!

rtel wrote on Tuesday, November 18, 2014:

I’m afraid we cannot directly support unofficial projects, or provide part specific information as we provide code for so many parts - all we could do is look up the information in the datasheet.

However, generically speaking, FreeRTOS Cortex-A projects are normally started from a standard C main() function, with its own interrupt handlers installed in the vector table. The vector table can be updated at run time, so it does not necessarily have to be built with the FreeRTOS interrupt handlers installed (for example the Zynq Cortex-A demo updates the vector base register when the kernel starts).

The standard C start up code would be called prior to main() being called. This normally sets up the stacks for the processor modes, clears .bss, copies initialised values, and can optionally enable the MMU and caches. Not much else. Code to do all this comes from the compiler vendor and/or chip vendor.

How and where the application gets loaded is very much application specific. The official demos just download directly to RAM and run from there from the start.


qwedvit wrote on Tuesday, November 18, 2014:

First of all, thank you for the quick response. I agree that there are simply to much hardware configurations to provide accurate information for all possible platforms.

If an official demo is downloaded into RAM isn’t it cleared from the RAM when a reset is applied to the circuit? Correct me if I’m wrong, but RAM is volatile and if I’m able to flash the FreeRTOS into RAM, I need to apply a reset in order to get the code running, thus the code will also be lost?

rtel wrote on Tuesday, November 18, 2014:

Yes - that is correct - the way the demos are provided is to download to RAM to allow the application to be developed and debugged, but not deployed as you rightly say the RAM will be cleared on a power cycle. Loading the image into RAM from any other source is somewhat dependent on the platform you have (NAND, SD Card, SPI flash, etc.). I would suggest looking at the software package that comes with the RSK, there will be examples in there that will boot from whatever interfaces are available on that hardware.


qwedvit wrote on Wednesday, November 19, 2014:

[SOLVED] I’ve managed to get the Blinky demo running from the FreeRTOS along with a QSPI bootloader. Now development on the FreeRTOS can really start!

[SOLUTION] In case anyone is having the same issues for this platform, I’d like to contribute my solution to the society :slight_smile:
set-up: RZ/A1H, QSPI flash chip used on Renesas RSK, no external RAM, DS-5, Eclipse, GCC compiler v13.01.

The binary output file of the FreeRTOS showed me a wrong start address, wrong end address and wrong execution start address. This seems to be locical as the FreeRTOS for the RZ in combination with the above mentioned developmentstudio was developed for the Renesas RSK. Therefore you need to add the following code at the end of the Start.S asembly file of the FreeRTOS which is located in {projdir}\Source\RenesasFiles\copmiler_specific\asm\

.word start /* pointer to the user application start address /
Used by NOR and SPI (RZ_A1H_xxxx_LOADER_RSK) */
.word end

.word execute /* execute address of first instruction */
.string “.BootLoad_ValidProgramTest.”

This code was copied from another sample project which was released by Renesas. When you’ve added this piece of code, you need to modify the linker file too as the compiler doesn’t know where the execute base address is located. Just add the following code between MEMORY{…} and SECTIONS{…}:

EXEC_BASE = 0x20040000; /* VECTOR_TABLE located here */

And add the following code within the parenthesis of SECTIONS{ add here }:

.reset EXEC_BASE :
	execute = .;
	*start.o (.text)
	.	= ALIGN(0x4);
} > RAM0L

This code is also copied from a working Renesas sample project. Right now I’ve got a combination of the two projects and are working on integrating the UARTs used by my prototype.

Thanks for the help! And keep up the good work!


rtel wrote on Thursday, November 20, 2014:

Thanks for taking the time to provide this information. I would really
appreciate it if you could also cut and paste this into the thread in
the FreeRTOS Interactive site from which you obtained the projects.
That way other people using the same project will see the information
when they download the code.