I’m getting into programming some of my critical code in FreeRTOS with the Atmel ARM 7 based SAM7X on my own board.
Some casual experimentation has resulted in some surprising results. When the standard demo web server is running, timing interrupts (i.e. those caused by the Timer) can be delayed by as much as 100ms - quite a lot for an RTOS!
I’m looking into this deeper, but as it stands it is difficult to contemplate running anything really RT.
Some discussion in this forum has hinted at the possibility of fixing this with nested interrupts, but would this really work? What if the long time periods are really code running as critical sections? Then there are no interrupts at all, presumably. So isn’t this whole thing a bit of a problem?
Could someone tell me if it’s stupid to try to fix this by using the FIQ interrupt and excluding fast interrupts from the Critical section and IQR enable disable macros?
There will be no need to context switch during my IRQ’s.
Thanks for any help.