the xISRStack needs to be 8 Byte aligned for PIC32 MZ EF with FPU and it is not 8 byte aligned.
Error occurs only when the hardware floating point option is released in the compiler.
The MIPS® Architecture For Programmers manual is written:
Restrictions: An AddressErrorException occurs if EffectiveAddress2…0 ≠ 0 (not doubleword-aligned).
Original FreeRTOS V9.00 Source: File port.c Line 192:
This problem was already noted, although the fix in not publicly
available yet. The relevant part of the updated code is below. I would
be grateful if you could try it and confirm it fixes your issue. The
original code is commented out, and the replacement code following
immediately after:
/* The stack used by interrupt service routines that cause a context
switch. 8
byte alignment is required to allow double word floating point stack pushes
generated by the compiler. */
//StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
StackType_t xISRStack[ configISR_STACK_SIZE ] __attribute__ ( ( aligned(
8 ) ) ) = { 0 };
/* The top of stack value ensures there is enough space to store 6
registers on
the callers stack, as some functions seem to want to do this. */
//const StackType_t * const xISRStackTop = &( xISRStack[
configISR_STACK_SIZE - 7 ] );
const StackType_t * const xISRStackTop = &( xISRStack[
configISR_STACK_SIZE - 8 ] );
this code fixed the issue and it’s semilar to my suggestion, excecpt the optional mask (configISR_STACK_SIZE & 0xFFFFFFFE). I have made this to ensure that any defenition of configISR_STACK_SIZE size will work. Default is 400 and it’s ok, but odd sizes may result in 4 Byte aligned top of stack. An additional information text in the FreeRTOSConfig.h would also be useful.