Memory ordering with FreeRTOS' CRITICAL_SECTION

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1

Hello,

Does following code ensure memory access ordering:

int value;

void test() {
        taskENTER_CRITICAL();
        value += 1;
        taskEXIT_CRITICAL();
}

since taskEXIT_CRITICAL() (vPortSetBASEPRI()) does not include any of the DMB, DSB instructions. (Let’s assume global value is then usded/modified within interrupt handler that would be disabled by portDISABLE_INTERRUPTS(). Also I am specifically considering ARM_CM4F port variant.)

Am I supposed to use my own/3rd party code (like C++’ std::atomic<T> ) to ensure so? If so, is that mentioned somewhere in FreeRTOS’ documentation?

Thank you.

Best Regards,
Stefan Misik

2

The barrier instructions are not needed between tasks and/ISRs on the same core (and presumably you are talking a single core processor), but to make sure that a “memory” operation, that would typically be to a memory-mapped I/O device, has taken place before you continue.

Within a single core, the processor will handle any ordering requirements to make instructions do what they are supposed to. You need the critical section as increasing value by 1 may take more that one instruction (you are going to read value, increment that value, and then put it back) and you don’t want another changing operation to happen in the middle of that.

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