FreeRtos in secure and Non-secure Region

Hi,
I am trying to toggle LED in FreeRtos task by enabling TrustZone in STM32cubeIDE .
I toggled LED in Non secure region.
When I did the debugging . it’s going to Infinite loop in the function prvInitialiseNewTask .
I used the default task given from STM32cubeIDE.

Can anyone help me overcome this issue.

void MX_FREERTOS_Init(void) {

  /* creation of defaultTask */
  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);

}

/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void *argument)
{
  /* USER CODE BEGIN defaultTask */
  /* Infinite loop */
  for(;;)
  {
	  HAL_GPIO_TogglePin(LED_GPIO_Port,LED_Pin);
	  osDelay(1);
  }
  /* USER CODE END defaultTask */
}

Are you running FreeRTOS on the secure side or on the non-secure side? Can you share your FreeRTOSConfig.h?

Hi Gaurav,
Thanks for replying to my post.
I want to use FreeRtos task exclusively in Non-secure region.
But due to some issue in STM32cubeIDE .I should enable Rtos in both secure and non-secure region.
Hence there are two FreeRTOSConfig.h for Secure and Non-Secure.
I am attaching both the files.
This is my Non-secure FreeRTOSConfig.h file

`/* USER CODE END Header */

#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H

/*-----------------------------------------------------------
 * Application specific definitions.
 *
 * These definitions should be adjusted for your particular hardware and
 * application requirements.
 *
 * These parameters and more are described within the 'configuration' section of the
 * FreeRTOS API documentation available on the FreeRTOS.org web site.
 *
 * See http://www.freertos.org/a00110.html
 *----------------------------------------------------------*/

/* USER CODE BEGIN Includes */
/* Section where include file can be added */
/* USER CODE END Includes */

/* Ensure definitions are only used by the compiler, and not by the assembler. */
#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
void xPortSysTickHandler(void);
#endif
#ifndef CMSIS_device_header
#define CMSIS_device_header "stm32h5xx.h"
#endif /* CMSIS_device_header */

/*-------------------- STM32H5 specific defines -------------------*/
#define configENABLE_TRUSTZONE                   1
#define configRUN_FREERTOS_SECURE_ONLY           0
#define configENABLE_FPU                         0
#define configENABLE_MPU                         0

#define configUSE_PREEMPTION                     1
#define configSUPPORT_STATIC_ALLOCATION          1
#define configSUPPORT_DYNAMIC_ALLOCATION         1
#define configUSE_IDLE_HOOK                      0
#define configUSE_TICK_HOOK                      0
#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
#define configTICK_RATE_HZ                       ((TickType_t)1000)
#define configMAX_PRIORITIES                     ( 56 )
#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
#define configMINIMAL_SECURE_STACK_SIZE          ((uint16_t)512)
#define configTOTAL_HEAP_SIZE                    ((size_t)8192)
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#define configMAX_TASK_NAME_LEN                  ( 16 )
#define configUSE_TRACE_FACILITY                 1
#define configUSE_16_BIT_TICKS                   0
#define configUSE_MUTEXES                        1
#define configQUEUE_REGISTRY_SIZE                8
#define configUSE_RECURSIVE_MUTEXES              1
#define configUSE_COUNTING_SEMAPHORES            1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
#define configUSE_TASK_NOTIFICATIONS             1
#define configHEAP_CLEAR_MEMORY_ON_FREE          0
#define configUSE_MINI_LIST_ITEM                 1
#define configUSE_SB_COMPLETED_CALLBACK          0
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed
   if lengths will always be less than the number of bytes in a size_t. */
#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */

#define configRUN_TIME_COUNTER_TYPE              size_t

/* Co-routine definitions. */
#define configUSE_CO_ROUTINES                    0
#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )

/* Software timer definitions. */
#define configUSE_TIMERS                         1
#define configTIMER_TASK_PRIORITY                ( 2 )
#define configTIMER_QUEUE_LENGTH                 10
#define configTIMER_TASK_STACK_DEPTH             128

/* CMSIS-RTOS V2 flags */
#define configUSE_OS2_THREAD_SUSPEND_RESUME  1
#define configUSE_OS2_THREAD_ENUMERATE       1
#define configUSE_OS2_EVENTFLAGS_FROM_ISR    1
#define configUSE_OS2_THREAD_FLAGS           1
#define configUSE_OS2_TIMER                  1
#define configUSE_OS2_MUTEX                  1

/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet             1
#define INCLUDE_uxTaskPriorityGet            1
#define INCLUDE_vTaskDelete                  1
#define INCLUDE_vTaskCleanUpResources        0
#define INCLUDE_vTaskSuspend                 1
#define INCLUDE_xTaskDelayUntil              1
#define INCLUDE_vTaskDelay                   1
#define INCLUDE_xTaskGetSchedulerState       1
#define INCLUDE_xTimerPendFunctionCall       1
#define INCLUDE_xQueueGetMutexHolder         1
#define INCLUDE_xSemaphoreGetMutexHolder     1
#define INCLUDE_uxTaskGetStackHighWaterMark  1
#define INCLUDE_xTaskGetCurrentTaskHandle    1
#define INCLUDE_eTaskGetState                1

/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
 /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
 #define configPRIO_BITS         __NVIC_PRIO_BITS
#else
 #define configPRIO_BITS         4
#endif

/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15

/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5

/* Interrupt priorities used by the kernel port layer itself.  These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )

/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
/* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
/* USER CODE END 1 */

#define SysTick_Handler xPortSysTickHandler

/* USER CODE BEGIN Defines */
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
/* USER CODE END Defines */

#endif /* FREERTOS_CONFIG_H */

This is my secure FreeRTOSConfig.h file

/* USER CODE END Header */

#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H

/*-----------------------------------------------------------
 * Application specific definitions.
 *
 * These definitions should be adjusted for your particular hardware and
 * application requirements.
 *
 * These parameters and more are described within the 'configuration' section of the
 * FreeRTOS API documentation available on the FreeRTOS.org web site.
 *
 * See http://www.freertos.org/a00110.html
 *----------------------------------------------------------*/

/* USER CODE BEGIN Includes */
/* Section where include file can be added */
/* USER CODE END Includes */

/* Ensure definitions are only used by the compiler, and not by the assembler. */
#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
void xPortSysTickHandler(void);
#endif
#ifndef CMSIS_device_header
#define CMSIS_device_header "stm32h5xx.h"
#endif /* CMSIS_device_header */

/*-------------------- STM32H5 specific defines -------------------*/
#define configENABLE_TRUSTZONE                   1
#define configRUN_FREERTOS_SECURE_ONLY           0
#define configENABLE_FPU                         0
#define configENABLE_MPU                         0

#define configUSE_PREEMPTION                     1
#define configSUPPORT_STATIC_ALLOCATION          1
#define configSUPPORT_DYNAMIC_ALLOCATION         1
#define configUSE_IDLE_HOOK                      0
#define configUSE_TICK_HOOK                      0
#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
#define configTICK_RATE_HZ                       ((TickType_t)1000)
#define configMAX_PRIORITIES                     ( 56 )
#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
#define configMINIMAL_SECURE_STACK_SIZE          ((uint16_t)512)
#define configTOTAL_HEAP_SIZE                    ((size_t)8192)
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#define configMAX_TASK_NAME_LEN                  ( 16 )
#define configUSE_TRACE_FACILITY                 1
#define configUSE_16_BIT_TICKS                   0
#define configUSE_MUTEXES                        1
#define configQUEUE_REGISTRY_SIZE                8
#define configUSE_RECURSIVE_MUTEXES              1
#define configUSE_COUNTING_SEMAPHORES            1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
#define configUSE_TASK_NOTIFICATIONS             1
#define configHEAP_CLEAR_MEMORY_ON_FREE          0
#define configUSE_MINI_LIST_ITEM                 1
#define configUSE_SB_COMPLETED_CALLBACK          0
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed
   if lengths will always be less than the number of bytes in a size_t. */
#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */

#define configRUN_TIME_COUNTER_TYPE              size_t

/* Co-routine definitions. */
#define configUSE_CO_ROUTINES                    0
#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )

/* Software timer definitions. */
#define configUSE_TIMERS                         1
#define configTIMER_TASK_PRIORITY                ( 2 )
#define configTIMER_QUEUE_LENGTH                 10
#define configTIMER_TASK_STACK_DEPTH             128

/* CMSIS-RTOS V2 flags */
#define configUSE_OS2_THREAD_SUSPEND_RESUME  1
#define configUSE_OS2_THREAD_ENUMERATE       1
#define configUSE_OS2_EVENTFLAGS_FROM_ISR    1
#define configUSE_OS2_THREAD_FLAGS           1
#define configUSE_OS2_TIMER                  1
#define configUSE_OS2_MUTEX                  1

/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet             1
#define INCLUDE_uxTaskPriorityGet            1
#define INCLUDE_vTaskDelete                  1
#define INCLUDE_vTaskCleanUpResources        0
#define INCLUDE_vTaskSuspend                 1
#define INCLUDE_xTaskDelayUntil              1
#define INCLUDE_vTaskDelay                   1
#define INCLUDE_xTaskGetSchedulerState       1
#define INCLUDE_xTimerPendFunctionCall       1
#define INCLUDE_xQueueGetMutexHolder         1
#define INCLUDE_xSemaphoreGetMutexHolder     1
#define INCLUDE_uxTaskGetStackHighWaterMark  1
#define INCLUDE_xTaskGetCurrentTaskHandle    1
#define INCLUDE_eTaskGetState                1

/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
 /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
 #define configPRIO_BITS         __NVIC_PRIO_BITS
#else
 #define configPRIO_BITS         4
#endif

/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15

/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5

/* Interrupt priorities used by the kernel port layer itself.  These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )

/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
/* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
/* USER CODE END 1 */

#define SysTick_Handler xPortSysTickHandler

/* USER CODE BEGIN Defines */
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
/* USER CODE END Defines */

#endif /* FREERTOS_CONFIG_H */

You likely are running FreeRTOS on the non-secure side. When you run FreeRTOS on the non-secure side, you need to run a small secure context management component on the secure side as well and that is why you see 2 FreeRTOSConfig.h files.

Can you try removing this line?

Hi Gaurav,
As suggested I commented the line #define SysTick_Handler xPortSysTickHandler and compiled.
I am still facing the same issue .
when I did the debugging from the function osKernelStart() In function prvInitialiseNewTask()
it’s going to the infinite loop.
Also is there any link how I can use FreeRtos for Secure and Non-secure in STM32CubeIDE

Have you enabled watchdog? If yes, can you disable it?

Here is the link explaining how to use FreeRTOS on ARMv8-M device - Using FreeRTOS on ARMv8-M Microcontrollers - FreeRTOS.

Watchdog is not enabled.
And in the above link there is no example explained for STM32CubeIDE ,is there any link for STM32cubeIDE specifically.

How did you verify it as in the image you shared, watchdog ISR seems to be getting triggered?

We have this one - GitHub - FreeRTOS/iot-reference-stm32u5. Which STM32 part are you using? Can you share your code?

Hi Gaurav ,
In my .ioc in STM32cubeIDE I have not enabled the watchdog.
image
In disassembly I am getting Cannot access memory


Can you install a different ISR for all the interrupts in the startup_stm32h563zitx.s file? This will help us figure out which interrupt is firing.

Hi Gaurav ,
I am very new to FreeRtos concept , I did not understand what do you mean by “install a different ISR for all the interrupts in the startup_stm32h563zitx.s file”
Can you elaborate on what I should do .

Forgive me if this has been already covered, but I see that the signal is received within a call to memcmp(), and the default interrupt handler is then invoked. The default signal handler contains Infinite_Loop.

Is it possible that there is a memory access violation or some other out-of-bounds addressing issue?

[edit]
Looking at more of the thread, I also see memset() and memcpy(); my guess is that the stack address that is being used is invalid in some way, leading to an attempt to access non-existent memory.

Can you share the startup_stm32h563zitx.s so that I can explain what I mean? Even better would be if you can share your complete code.

Hi Gaurav,
Thank you for replying to my post .
I am not able to attach .s file so I changed the same startup_stm32h563zitx.s file extension to .c and attached.
Non secure startup_stm32h563zitx.s
startup_stm32h563zitx.c (17.9 KB)
Nonsecure-main file

#include "main.h"
#include "cmsis_os2.h"


void SystemClock_Config(void);
void MX_FREERTOS_Init(void);
static void MX_GPIO_Init(void);
static void MX_GTZC_NS_Init(void);

int main(void)
{

  HAL_Init();
  SystemClock_Config();
  /* GTZC initialisation */
  MX_GTZC_NS_Init();
  MX_GPIO_Init();
  osKernelInitialize();
  MX_FREERTOS_Init();
  osKernelStart();
  while (1)
  {

  }

}

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 5;
  RCC_OscInitStruct.PLL.PLLN = 96;
  RCC_OscInitStruct.PLL.PLLP = 2;
  RCC_OscInitStruct.PLL.PLLQ = 2;
  RCC_OscInitStruct.PLL.PLLR = 2;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
  RCC_OscInitStruct.PLL.PLLFRACN = 0;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_PCLK3;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
  {
    Error_Handler();
  }
}
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  __HAL_RCC_GPIOB_CLK_ENABLE();
  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin : LED_Pin */
  GPIO_InitStruct.Pin = LED_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
}

startup_stm32h563zitx.c (17.9 KB)

secure main file

#include "main.h"
         mapped in the non-secure vector table                             */

#define VTOR_TABLE_NS_START_ADDR  0x08100000UL


static void NonSecure_Init(void);
static void MX_GPIO_Init(void);
static void MX_GTZC_S_Init(void);
static void MX_ICACHE_Init(void);


/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{

  HAL_Init();

  MX_GTZC_S_Init();

  MX_GPIO_Init();
  MX_ICACHE_Init();


  NonSecure_Init();

  while (1)
  {
  }

}

static void NonSecure_Init(void)
{
  funcptr_NS NonSecure_ResetHandler;

  SCB_NS->VTOR = VTOR_TABLE_NS_START_ADDR;

  /* Set non-secure main stack (MSP_NS) */
  __TZ_set_MSP_NS((*(uint32_t *)VTOR_TABLE_NS_START_ADDR));

  /* Get non-secure reset handler */
  NonSecure_ResetHandler = (funcptr_NS)(*((uint32_t *)((VTOR_TABLE_NS_START_ADDR) + 4U)));

  /* Start non-secure state software application */
  NonSecure_ResetHandler();
}

static void MX_GTZC_S_Init(void)
{


  MPCBB_ConfigTypeDef MPCBB_Area_Desc = {0};
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_USART3, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_UCPD1, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_USB, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_LPUART1, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_I2C3, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_ETHERNET, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_ADC12, GTZC_TZSC_PERIPH_SEC|GTZC_TZSC_PERIPH_NPRIV) != HAL_OK)
  {
    Error_Handler();
  }
  MPCBB_Area_Desc.SecureRWIllegalMode = GTZC_MPCBB_SRWILADIS_ENABLE;
  MPCBB_Area_Desc.InvertSecureState = GTZC_MPCBB_INVSECSTATE_NOT_INVERTED;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[0] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[1] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[2] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[3] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[4] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[5] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[6] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[7] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[8] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[9] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[10] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[11] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[12] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[13] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[14] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[15] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[16] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[17] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[18] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_SecConfig_array[19] =   0x00000000;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[16] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[17] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[18] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[19] =   0xFFFFFFFF;
  MPCBB_Area_Desc.AttributeConfig.MPCBB_LockConfig_array[0] =   0x00000000;
  if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_Area_Desc) != HAL_OK)
  {
    Error_Handler();
  }

}

You’ll see that in this file, there is a vector table g_pfnVectors which has entries for all the ISRs (for example, WWDG_IRQHandler). You will also see that all the ISRs are currently defined to Default_Handler in the lines looking like the following:

	.weak	WWDG_IRQHandler
	.thumb_set WWDG_IRQHandler,Default_Handler

Instead of setting every handler to Default_Handler, create a separate handler for each ISR. You need to do the following for each ISR:

  1. Remove the lines which set the ISR to Default_Handler:
    .weak	WWDG_IRQHandler
    .thumb_set WWDG_IRQHandler,Default_Handler
    
  2. Create a separate ISR:
    .section .text.WWDG_IRQHandler,"ax",%progbits
    WWDG_IRQHandler:
        b WWDG_IRQHandler
     .size WWDG_IRQHandler, .-WWDG_IRQHandler
    

After doing that, you’ll be able to determine which interrupt is firing.

Hi Gaurav
I made the changes ,I am getting output as USB_DRD_FS_IRQHandler .

Did you make the above change for all the ISRs or just the WWDG_IRQHandler? Can you share the file with your changes?

I commented .weak WWDG_IRQHandler
and added .section in the begging.
I attached my stm32h563zitx.s file
startup_stm32h563zitx.c (18.1 KB)

Thank You.

Please read my message. You need to follow the same pattern for each ISR. In other words, do what you did for WWDG_IRQHandler for all the following ISRs:

	NMI_Handler
	HardFault_Handler
	MemManage_Handler
	BusFault_Handler
	UsageFault_Handler
	SecureFault_Handler
	DebugMon_Handler
	WWDG_IRQHandler
	PVD_AVD_IRQHandler
	RTC_IRQHandler
	RTC_S_IRQHandler
	TAMP_IRQHandler
	RAMCFG_IRQHandler
	FLASH_IRQHandler
	FLASH_S_IRQHandler
	GTZC_IRQHandler
	RCC_IRQHandler
	RCC_S_IRQHandler
	EXTI0_IRQHandler
	EXTI1_IRQHandler
	EXTI2_IRQHandler
	EXTI3_IRQHandler
	EXTI4_IRQHandler
	EXTI5_IRQHandler
	EXTI6_IRQHandler
	EXTI7_IRQHandler
	EXTI8_IRQHandler
	EXTI9_IRQHandler
	EXTI10_IRQHandler
	EXTI11_IRQHandler
	EXTI12_IRQHandler
	EXTI13_IRQHandler
	EXTI14_IRQHandler
	EXTI15_IRQHandler
	GPDMA1_Channel0_IRQHandler
	GPDMA1_Channel1_IRQHandler
	GPDMA1_Channel2_IRQHandler
	GPDMA1_Channel3_IRQHandler
	GPDMA1_Channel4_IRQHandler
	GPDMA1_Channel5_IRQHandler
	GPDMA1_Channel6_IRQHandler
	GPDMA1_Channel7_IRQHandler
	IWDG_IRQHandler
	ADC1_IRQHandler
	DAC1_IRQHandler
	FDCAN1_IT0_IRQHandler
	FDCAN1_IT1_IRQHandler
	TIM1_BRK_IRQHandler
	TIM1_UP_IRQHandler
	TIM1_TRG_COM_IRQHandler
	TIM1_CC_IRQHandler
	TIM2_IRQHandler
	TIM3_IRQHandler
	TIM4_IRQHandler
	TIM5_IRQHandler
	TIM6_IRQHandler
	TIM7_IRQHandler
	I2C1_EV_IRQHandler
	I2C1_ER_IRQHandler
	I2C2_EV_IRQHandler
	I2C2_ER_IRQHandler
	SPI1_IRQHandler
	SPI2_IRQHandler
	SPI3_IRQHandler
	USART1_IRQHandler
	USART2_IRQHandler
	USART3_IRQHandler
	UART4_IRQHandler
	UART5_IRQHandler
	LPUART1_IRQHandler
	LPTIM1_IRQHandler
	TIM8_BRK_IRQHandler
	TIM8_UP_IRQHandler
	TIM8_TRG_COM_IRQHandler
	TIM8_CC_IRQHandler
	ADC2_IRQHandler
	LPTIM2_IRQHandler
	TIM15_IRQHandler
	TIM16_IRQHandler
	TIM17_IRQHandler
	USB_DRD_FS_IRQHandler
	CRS_IRQHandler
	UCPD1_IRQHandler
	FMC_IRQHandler
	OCTOSPI1_IRQHandler
	SDMMC1_IRQHandler
	I2C3_EV_IRQHandler
	I2C3_ER_IRQHandler
	SPI4_IRQHandler
	SPI5_IRQHandler
	SPI6_IRQHandler
	USART6_IRQHandler
	USART10_IRQHandler
	USART11_IRQHandler
	SAI1_IRQHandler
	SAI2_IRQHandler
	GPDMA2_Channel0_IRQHandler
	GPDMA2_Channel1_IRQHandler
	GPDMA2_Channel2_IRQHandler
	GPDMA2_Channel3_IRQHandler
	GPDMA2_Channel4_IRQHandler
	GPDMA2_Channel5_IRQHandler
	GPDMA2_Channel6_IRQHandler
	GPDMA2_Channel7_IRQHandler
	UART7_IRQHandler
	UART8_IRQHandler
	UART9_IRQHandler
	UART12_IRQHandler
	SDMMC2_IRQHandler
	FPU_IRQHandler
	ICACHE_IRQHandler
	DCACHE1_IRQHandler
	ETH_IRQHandler
	ETH_WKUP_IRQHandler
	DCMI_PSSI_IRQHandler
	FDCAN2_IT0_IRQHandler
	FDCAN2_IT1_IRQHandler
	CORDIC_IRQHandler
	FMAC_IRQHandler
	DTS_IRQHandler
	RNG_IRQHandler
	HASH_IRQHandler
	CEC_IRQHandler
	TIM12_IRQHandler
	TIM13_IRQHandler
	TIM14_IRQHandler
	I3C1_EV_IRQHandler
	I3C1_ER_IRQHandler
	I2C4_EV_IRQHandler
	I2C4_ER_IRQHandler
	LPTIM3_IRQHandler
	LPTIM4_IRQHandler
	LPTIM5_IRQHandler
	LPTIM6_IRQHandler

Or just read the Interrupt state register with a debugger while breaking in the default handler
https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/interrupt-control-and-state-register

Note at VECTACTIVE:

Subtract 16 from this value to obtain the CMSIS IRQ number

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