FreeRTOS for Renesas RCAR R7 Core

I tried searching for FreeRTOS for R7 core, which is found in Renesas RCAR V3H/H3 boards, but didn’t get any. Are there any sources available for running FreeRTOS in the R7 core of these boards?


I don’t think this has been ported to the R7 in the public domain. I have done it commercially on an R-CAR. The R7 is fairly similar to the R5, the key difference is that the R7 complex has a built in GIC. I think you will have to implement this yourself based on the R5. The R-CAR H3 is a complex processor to work with. I think the only debuggers which support it are the ARM DStream and Lauterbach.

A little more info on RealtimeRik’s reply. There is a Renesas Cortex-R port that you may be able to use as a base here: - there are other ports to the R5 too - for example the Cortex-R cores in the Zynq Ultrascale examples.

As RealtimeRik eludes too - the biggest difference between these R cores is going to be the interrupt controller - which may also be from ARM (the ARM GIC), or proprietary. If it is a standard GIC, which it doesn’t sound like it is, then you can probably just use the Ultrascale Cortex-R port (which is GCC, if that is what you need), otherwise you may need to do some customisation to the GIC. This is similar to the Cortex-A cores, where we have instructions for when the ARM GIC is used and for when a proprietary GIC is used.

@rtel It is a standard GIC (ARM GIC v1.0 compliant). The R7 Core used in the RCAR is an ARM Cortex-R7-MPCore which includes the GIC. In fact I am not sure if it exists in the wild in any other form than the MPCore.

Thank you @RealtimeRik and @rtel for responding. So what you are suggesting is modifying the R5 FreeRTOS kernel port (in Ultrascale Cortex-R port) to incorporate the GIC, right? The RCAR R7 core has a standard GIC which is ARM GIC v2 compliant.

I think the Ultrascale port also has a standard GIC so you should be able to use that port. Can’t be certain as I’ve never use the RCAR part myself.