FreeRTOS : Cache Invalidation when Task Switching on ARM Corterx CM7

Kernel
1

balajisubrcyp wrote on Monday, April 02, 2018:

Hi All,

I have an issue in FreeRTOS 9.0.0, when I am sending IPERF udp traffic with data rate set at 20Mbps, I see the Hard faults on ARM Corter CM7. The my_HardFault_Handler is caused by an
DataBus Error (ie. Data bus fault occurred but details have been lost due to
priorities delaying processing of the faults…) with imprecise error bit set.

SCB_CFSR_IMPRECISERR.

If I invalidate the ICache and DCache in port.c the problem of hard fault is not seen…

here is the below code…

/*

  • See header file for description.
    /
    BaseType_t xPortStartScheduler( void )
    {
    /     configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
    See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

    SCB_InvalidateICache();
    SCB_InvalidateDCache();

    I haven’t seen any fixes in FreeRTOS for invalidate cache while task switching… is this really bug??

    Thanks
    Balaji.

2

rtel wrote on Monday, April 02, 2018:

Is the Ethernet using DMA? We have generally found that, if that is the
case, the easiest thing to do is to ensure the memory used by the DMA is
marked as non-cacheable - otherwise you will have two memory bus masters.

3

balajisubrcyp wrote on Monday, April 02, 2018:

Hi Richard,

This is STM32H7 MCU intefacing with ARM cortex CM4 via SDIO bus. ARM CM4 is a Wifi Chip receiving Data from the Host STM32H7MCU.

The buffer used a for the transfer is a global buffer aligned (on receive ) side…

ALIGNED_PRE(4) static uint8_t temp_dma_buffer[ MAX( 2 * 1024, MTU_SIZE+ 64 ) ] ALIGNED(4);

Do you know how to mark this data non-cacheable in FreeRTOS…

Also while writing data we use allocated buffer from heap…(TX) is there any way to mark some section of memory from heap as Non-Cacheable… using FreeRTOS-lwip stack…

Thanks
Balaji.

4

rtel wrote on Tuesday, April 03, 2018:

Do you know how to mark this data non-cacheable in FreeRTOS…

It is not a FreeRTOS configuration, but an MCU configuration. The easiest way to do it is to place the network buffers in a known memory location, then mark that memory as non cachable in the C start up code. I think the Zynq demo does this already so you could use that as a reference.

5

balajisubrcyp wrote on Tuesday, April 03, 2018:

Hi Richard,

I have found the MPU regions to mark them as non cacheable. This could be pointed to heap memory location ( for packet pools)

Thanks You for your support
Balaji.