Found bug in FreeRTOS port for Microchip PIC2

adamjcasey wrote on Tuesday, October 20, 2009:

Just wanted to pass along a bug I found in the port for the PIC24H (from version FreeRTOSV5.4.2.)

The _vPortYield assembly subroutine was putting #32 into the SR to disable interrupts.  However, this sets the CPU Interrupt Priority Level Status to level 1.  This certainly disables the tick (which is set to priority 1 in the port) but not any other user settable interrupts.  Since the default for the PIC is priority 4, this caused me to experience corruption in my context switches when tested under load.

I changed it to set the CPU Interrupt Priority Level Status to level 7.  This masks ALL user interrupts.  I assume this is how it was intended to behave?

Line 56 of the portasm_PIC24.s file should change from:

MOV #32, SR


MOV #224, SR

Also, page 16 of this document describes the register in question (just for your info.)

edwards3 wrote on Tuesday, October 20, 2009:

Please read the section about configKERNEL_INTERRUPT_PRIORITY on the following page: and note that only functions that have FromISR() in their name can be called from interrupts above that priority. I think you have fixed a bug that does not exist.

adamjcasey wrote on Wednesday, October 21, 2009:

Thanks for the reply.  I read this link and it was informative.  However, I still have a problem with it for the following reasons:

1. The configKERNEL_INTERRUPT_PRIORITY constant is not reflected in the assembly file.  It is hard coded to CPU priority 1.
2. Perhaps there are good reasons for making a critical section ‘interruptible’, but I would argue that this is never the case during a *context switch*.  This should undoubtedly be atomic.
3. If this is indeed an intended feature, then perhaps the kernel interrupt priority should default to the *most safe* priority of 7.  Or at least the default for all the interrupt sources in the PIC24, which is 4

I’m new to FreeRTOS but not RTOSes in general, so perhaps I don’t understand the utility of being able to interrupt a context swtich.

rtel wrote on Wednesday, October 21, 2009:

The page that edwards3 linked to contains the following text: "Unfortunately, due to limitations in the GCC inline assembler, modifications to this value will necessitate a small update to the port source code with respect to the interrupt mask value (accessed by inline assembler instructions)."  The value it refers to is configKERNEL_INTERRUPT_PRIORITY.  Also, I’m not sure the statement still holds true and the constant could probably be used indirectly in the asm file now, although this may make it less efficient.

It is not normal to have configKERNEL_INTERRUPT_PRIORITY set to anything other than the lowest priority level.  The PIC24 port allows interrupt nesting, but not a full nesting model as per the ports that also have configMAX_SYSCALL_INTERRUPT_PRIORITY defined (such as the PIC32 port).  Therefore interrupt above configKERNEL_INTERRUPT_PRIORITY cannot cause a context switch, as you rightly point out.  Again quoting from the linked page "However, such ISR’s cannot use the API functions". 

Hope this clarifies things.


adamjcasey wrote on Wednesday, October 21, 2009:

It does indeed clarify things.  I’m glad that it was a designed feature and not a bug.