Just wanted to pass along a bug I found in the port for the PIC24H (from version FreeRTOSV5.4.2.)
The _vPortYield assembly subroutine was putting #32 into the SR to disable interrupts. However, this sets the CPU Interrupt Priority Level Status to level 1. This certainly disables the tick (which is set to priority 1 in the port) but not any other user settable interrupts. Since the default for the PIC is priority 4, this caused me to experience corruption in my context switches when tested under load.
I changed it to set the CPU Interrupt Priority Level Status to level 7. This masks ALL user interrupts. I assume this is how it was intended to behave?
Line 56 of the portasm_PIC24.s file should change from:
MOV #32, SR
MOV #224, SR
Also, page 16 of this document describes the register in question (just for your info.)