saiberion wrote on Monday, September 24, 2007:
MCK = 44MHz
SPI Mode Register is initialised with 0x0A000015 meaning master mode, fixed peripheral, CS lines connected to decoder, mode fault detection disabled, no loopback and delay between chip selects = 10/MCK.
All four CS registers are initialised with 0x00010202 meaning inactive state of SCK is logic zero, data captured on leading edge and changed on following, CS lines rise after last transfer, 8 bit transfers, SCK = MCK/2 (about 22MHz fr me), delay before SCK = 1/MCK, no delay between transfers on same CS.
For sending and receiving data the PDC is used.
And now the crucial part. The decoder is a PLD that either forwards corresponding CS signals to dataflash, a DAC and 3 ADCs or handles the MISO/MOSI lines for 8 bit write or read-only registers. These registers use 1 byte transfer, the DAC needs 3-byte transfer and the ADCs work with 2-byte transfers.
For single transfers all works fine so far but 2 of the ADCs shall work as transient recorder that store measured data in dataflash and so i can’t afford having to much delay between spi transfers.
The first byte sent to ADC is a control byte for initialising the next mesurement. At the same time the first byte of the last result is transferred. The second byte of the measure result comes with the next 8 clocks (I simply resend control byte). Then when CS for ADC is inactive it starts converting which lasts up to 3.5us. Now I’d like to initialise the next conversion und get the recent one but now there is a delay of nearly the kernel tick period (my kernel tick is 66us).
I think that’s more than enough information and while writing this I got an idea I’m going to try out now