Can I implement SMP with Cortex-R5F dual core in zynqultraScale+ mpsoc?

If SMP implementation of FreeRTOS is possible, how should I modify it?
Is there another example?

Currently there is an SMP branch of FreeRTOS at this location: GitHub - FreeRTOS/FreeRTOS-Kernel at smp
There are a few ports available. The RP2040 is a good device to use as a reference to an SMP port.

The Cortex-R5 devices I have seen so far do not have unified RAM so they are best suited for AMP implementations. Essentially an AMP is a separate copy of FreeRTOS running on each core. If your R5 system unifies the RAM, then SMP will likely work with some porting.

Thank you so much for your explanation.
Does the case of R5 system unifies RAM mean a change in the chip?
Why use unified RAM to use FreeRTOS?
If RAM is not unifies, is there any way to implement it in FreeRTOS?

The SMP version of FreeRTOS schedules tasks to ALL cores in the system. That requires that the each core have access to the memory required by any task. Even the kernel task list must be shared between the cores. This requirement forces each R5 to have full access to ALL the memory.

If the R5’s do not have shared access to all the memory, then you can run 1 instance of FreeRTOS on each R5. Tasks will only run on a single R5. In effect you will have multiple applications running and each application will have its own copy of FreeRTOS. In this system, any communication between R5 applications will need to be handled with special features in that SOC.

For Xilinx ultrasound + MPSoC, R5 is the memory of the TCM.
After checking the Xilinx sheet, TCM is divided into A and B.
Can I use FreeRTOS if I unify this memory?
Also, does using DDR as a shared memory have any performance problems?
The A53 core is also used as Linux in DDR memory.

This is the Zynq UltraScale+ MPSoC Software Developer’s Guide.
There is no other word about why XILINX can’t apply for.

My guess is that the memories can’t both be TCM for both processors at the same time. That would need arbitration logic that would make it hard to be Tightly Coupled.

Normally, sharing a memory between processors will add delays to its access, and DDR also normally has a delay in accessing it

Reading the details of RPU in this document, I do not thin is possible to unify.

Likely. The recommendation from Xilinx is to use TCM -

There are two TCM interfaces that permit connection to configurable memory blocks of tightly-coupled memory (ATCM and BTCM).

•An ATCM typically holds interrupt or exception code that must be accessed at high speed, without any potential delay resulting from a cache miss.

•A BTCM typically holds a block of data for intensive processing, such as audio or video processing.

Would you please elaborate on why do you want to use SMP? What is the problem that you are trying to solve?

We are going to use CAN communication and various interfaces for the Cortex-R5F core. In terms of performance, I think you can show higher performance when you use two rather than one. Therefore, I want to operate as SMP.

[Sharing memory between processors typically adds a delay in access, and DDRs also typically experience a delay in access]
The key to what I want to know is the text above. I want to know exactly why.

Why is it delayed when shared?
Will it be delayed if I use DDR?

This question is very specific to Xilinx hardware and I’d recommend reaching out to them as they would be able to provide accurate information.