ARM Cortex-A9 FreeRTOS_IRQ_Handler

kamejoko80 wrote on Monday, February 20, 2017:

Hello everyone,

Regarding to ARM cortex-a9 porting, I see the IRQ handler as below code :

FreeRTOSv9.0.0\FreeRTOS\Source\portable\GCC\ARM_CA9\portASM.S

.align 4
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:

...

	/* Call the interrupt handler. */
	PUSH	{r0-r3, lr}
	LDR		r1, vApplicationIRQHandlerConst
	BLX		r1
	POP		{r0-r3, lr}
	ADD		sp, sp, r2

	CPSID	i
	DSB
	ISB
    
....

This code intends to allow nested interrupt but IRQ enable instruction “CPSID i” is bellow application IRQ handler, I think this is not correct. In order to higher priority IRQ can preamt lower priority IRQ, IRQ enable instruction should be placed before application IRQ handler.


...

   /* save registers */
	PUSH	{r0-r3, lr}
    
	CPSID	i
	DSB
	ISB

	/* Call the interrupt handler. */
	LDR		r1, vApplicationIRQHandlerConst
	BLX		r1
    
	POP		{r0-r3, lr}
	ADD		sp, sp, r2
 
....

Please correct me if I’m wrong.

Thanks and Best Regards,
Phuong Dang

rtel wrote on Monday, February 20, 2017:

This code intends to allow nested interrupt but IRQ enable instruction
“CPSID i” is bellow application IRQ handler, I think this is not
correct. In order to higher priority IRQ can preamt lower priority IRQ,
IRQ enable instruction should be placed before application IRQ handler.

The IRQ enable instruction is in the application IRQ handler. It is
done that way to allow the application writer to decide if they want an
interrupt to be nestable or not. CPSID i is disabling the IRQ again,
not enabling it, which is why it appears after the application handler.

kamejoko80 wrote on Monday, February 20, 2017:

Hello FreeRTOS,

Got it,

Sorry for my miss reading regarding to CPSID i command.
Thanks so much for your quick reply.

Best regards