ZYNQ7000 + AXI INTC + PS Interrupts + FreeRTOS

Partners & Sponsors Xilinx
1

Hello forum,

I am working with Vivado/SDK2019.1

I am creating a project based on the FreeRTOS +Tcp and Fat demo on a Zynq7020. All is working fine. I also added my own hardware file including PL-PS interrupts from Vivado. I am using the xInterruptController instance defined by FreeRTOS to handle the interrupts as described in many post. Still, everything working fine. I added a video processing pipeline to my hardware design, which I tested in a bare metal application and verified that it is working correctly. Also, fine.

Here comes the problem:

I can only connect 16 interrupts (with a concat block) to the PS and my design by now needs more than that. One solution that I have found is to use a Concat + AXI interrupt core tied to the PS like so:

https://support.xilinx.com/s/article/1165154?language=en_US

Now I am a little confused about what might be the way to use the AXI INTC instance and the XinterruptController instance needed by FreeRTOS together. If I launch the application on my hardware I still get the +tcp and fat demo to run, context switching happens and I can use interrupts coming from the PS (I2C) but the interrupts coming from the PL do not get serviced anymore.

The hardware is working as it is supposed to which I confirmed with an integrated logic analyzer. E.g. a gpio instance detects a change on an input and asserts its interrupt line. The Axi Interrupt Controller receives the signal through the concat block and asserts its interrupt output as well. Using the debugger in SDK confirms that the Axi INTC core is configured and working properly by reading the master enable register and interrupt pending register. Also, the vector table entries seem to match but the ISR do not execute. WHY?

Can someone please explain what would be the best way to solve this. What am I missing?

Thank you in advance!

2

If interrupts numbers higher than 16 work outside of a FreeRTOS application, do you know at what point in the FreeRTOS initialisation code they stop working?

3

Its been a while since I worked with a Zynq part, but as I remember, the AXI INTC was just a standard interrupt expander. Note, that as far as the processor is concerned, all the interrupts attached to it are just one interrupt, and the vector for that interrupt will go to a handler for the INTC, that looks at the module, finds out which of the input is requesting, and then THAT code vectors to the appropriate “ISR” function, that may have somewhat different rules for how to write it. (I forget if the Zync has a vector interrupt controller or just a single interrupt pin with a software vector handler).

Note, that interrupts on the expander controller have more spots that they need to be enabled, the input to the CPU has an enable for the full interrupt expander, the device has its own enables for generating the interrupts, and most expanders like this have a per-input enable that also needs to be set.

4

Hello, i’ve seen this post looking around-
The Zynq7000 has the GIC interrupt controller from ARM, which multiplexes other interrupt inside the unique IRQ line to the core; a software handler reads GIC register and redirect to the correct vector.
This is already built in the Xilinx bsp,

5

Thank you all for your input. I will do some testing and report back once I found something that helps to solve the issue.