I am working with Vivado/SDK2019.1
I am creating a project based on the FreeRTOS +Tcp and Fat demo on a Zynq7020. All is working fine. I also added my own hardware file including PL-PS interrupts from Vivado. I am using the xInterruptController instance defined by FreeRTOS to handle the interrupts as described in many post. Still, everything working fine. I added a video processing pipeline to my hardware design, which I tested in a bare metal application and verified that it is working correctly. Also, fine.
Here comes the problem:
I can only connect 16 interrupts (with a concat block) to the PS and my design by now needs more than that. One solution that I have found is to use a Concat + AXI interrupt core tied to the PS like so:
Now I am a little confused about what might be the way to use the AXI INTC instance and the XinterruptController instance needed by FreeRTOS together. If I launch the application on my hardware I still get the +tcp and fat demo to run, context switching happens and I can use interrupts coming from the PS (I2C) but the interrupts coming from the PL do not get serviced anymore.
The hardware is working as it is supposed to which I confirmed with an integrated logic analyzer. E.g. a gpio instance detects a change on an input and asserts its interrupt line. The Axi Interrupt Controller receives the signal through the concat block and asserts its interrupt output as well. Using the debugger in SDK confirms that the Axi INTC core is configured and working properly by reading the master enable register and interrupt pending register. Also, the vector table entries seem to match but the ISR do not execute. WHY?
Can someone please explain what would be the best way to solve this. What am I missing?
Thank you in advance!