Dear Mr. rtel
This is the continuing topic of the following topic.
Zynq Ultrascale MPSoC task floating point corruption
I started this new topic because this forum restricts new user to post only three times in the same topic.
The overhead is both in time and stack usage - whether that is an issue for you is very much dependent on the application you are writing. These devices can have a lot of RAM.
Yes, my device has enough RAM. It means stack usage is not problem. I will estimate time overhead.
It is unexpected that you need to save all the floating point registers on interrupt entry
I analyzed disassembled code for my floating point operations in interrupt. I found that s0, s1 and s2 registers are used in those operations. Does it mean v0-v2 require to be saved on IRQ entry?
I need to compile some code to see what it is doing. We have a Zynq project that uses Vitis and runs in QEMU now too
Thank you very much for an investigation on your side. I am using Xilinx SDK 2019.1 instead of Vitis. Compiler is GCC which is built in Xilinx SDK. Maybe it is almost same as compiler in Vitis. Thank you for your support!
Wat