samkings wrote on Tuesday, November 24, 2015:

In the Zynq port of FreeRTOS (V8.1.2) the value of portLOWEST_USABLE_INTERRUPT_PRIORITY is defined as:


As I understand it, the Zynq supports 32 levels of interrupt priority, from 0 (highest) to 31 (lowest).
However FreeRTOS defines the lowest usable priority as 30, not 31. Why is this?

The FreeRTOS_Tick_Handler is driven by the CPU Private Timer, which generates a Private Peripheral Interrupt with IRQ #29, and the interrupt controller (GIC) is then configured to assign a priority of portLOWEST_USABLE_INTERRUPT_PRIORITY (30) to this interrupt. I don’t understand why this has to be priority 30 and not priority 31?

I tried changing the priorty to 31 and, not suprisingly, the FreeRTOS scheduler didn’t run.

I’ve read the Zynq Technical Reference Manual chapters on Interrupts and Timers and I don’t see any mention of the interrupt priorty 31 being unusable.

It’s just an academic quesion, but I’d like to understand why priority 31 is unusable?

Regards, Sam.

rtel wrote on Tuesday, November 24, 2015:

I can’t remember the exact details. The Zynq uses a generic ARM GIC (generic interrupt controller), so the information you need is much more likely to be found in the GIC documentation than the Zynq documentation.

It may be something to do with priority masking. Critical sections uses the ICCPMR (priority mask register) to mask a subset of interrupt, rather than globally disable all interrupts. If you write 0 to the PMR, then all interrupts are masked. If you write 255 to the PMR then you unmask (enable) as many priorities are possible, but 255 will, when you take into account the implemented bits, equate to 31, hence it might be simply that priority 31 can never be enabled…this might be wrong though so take a look at the documentation.


samkings wrote on Tuesday, November 24, 2015:

Ah ha, thanks for the info. I had a quick read of the GIC Spec, it says “The GIC always masks an interrupt that has the largest supported priority field value. This provides an additional means of preventing an interrupt being signalled to any processor.”

They seem to be suggesting it is useful a tool to be able to mask out any individual interrupt, without changing any code, other than the assigned priority. I think I can see the benefit of this.

Cheers, Sam.