Sorry I’m new to TCP.
I’m trying to setup FREE RTOS + TCP on a custom board using xilinx ultrascale + TI DP83822 PHY.
The application runs on A53 core 0.
My starting point was the Free RTOS example we can generate using the SDK to set up the OS.
Once working I imported the the FREE RTOS + TCP package specific to xilinx ultrascale. I took one matching my OS version / version 180821.
I modified the PHY init to match my device (which is only capable of 100Mbds).
The board is using GEM3 controller.
The IP stack seems initialize OK then go to process a network down event were it initialize the PHY.
From there , when Link is detected up by the PHY, a UDP socket is created and bound to port 0x8000.
Every second a message is sent by the application.
I can see the code going to the emacps_send_message wich triggers emacps_send_message interrupt.
I cannot see any signal at PHY input.
Same on the receive side, the PHY RX signals seem valid but not receive interrupt event is generated.
Checking HW with HW team, all looks ok…
Did somebody already had this combination of GEM / PHY ?
Most interesting post so far was FreeRTOS + TCP/IP on Arm Cortexa53
Still seems most of the changes are in the package I imported.
I’ve been stuck on it for a week now looking at a lot resource I could find on internet but I could not figure out what is the problem.
Any pointer would be greatly appreciated.