Why we need to enable data cache at the main on zynq7020?


Im using FreeRTOS on zynq7020. In boot.S file of Zynq SDK, CRValMmuCac value is 0x1005 which means enabling icache, dcache and MMU. Also in the same file L2CCControl variable is 1 which means enable L2 cache. Despite these, in zynq demo of 160919 FreeRTOS lab project, code start with Xil_DCacheEnable() function. I didn’t call this function at first, but then I realized that I really need to call this function. What am I missing?

Have a good day.

Note: In Vitis’s “Registers” view, I can observe cp15:C1:sctlr register 'or’ed with 0x1005 after runnning the “mcr p15,0,r0,c1,c0,0” line and l2cache:reg1control is change to 1 after running “enable the L2 caches” line.

Hi @ozanagma,
Sorry for the late reply, I will see if I can find someone to help you.
Jason Carroll

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Hi - I would like to make sure I understand your question. Are you saying the C startup code appears to enable the D cache, but the D cache don’t actually get enabled unless you call Xil_DCacheEnable()?

If that is the case, what happens to the D cache bits in the control register when the C startup code attempts to enable it? Do you see it getting enabled, but later disabled?

I’m pretty sure the caches are enabled in boot.S. I tested it with zc702. I was getting an cache error while invalidating cache , I thought it had something to do with enabling the cache at the main. But I was wrong about this. Now I think we don’t need to use cache enable function in main. But still, calling this function in the sample project made me skeptical. Is there any particular reason why this function is called in main? Or was it put by saying that cache should be enabled if it was not enabled somehow?

That is a relatively old demo so can only really speculate. Maybe the C startup code is different now and previously the cache wasn’t enabled on entry to main(). The only time we really had to play around with the cache was when running TCP/IP applications that needed the DMA buffers in uncached memory.