FreeRTOS 7.4.2, Atmel SAM3U (ARM Cortex-M3), Atmel Studio 6.1
HI there, I am working on modifying the SAM4L low-power tickless idle implementation (from the demo) for the SAM3U and I’m finding the comments around the interrupt disable confusing in the demo version of
// Enter a critical section but don't use the taskENTER_CRITICAL() method as // that will mask interrupts that should exit sleep mode. __asm volatile( "cpsid i \n\t" "dsb \n\t" );
Essentially the same thing shows up in the standard CM3 port code.
If I understand the assembly correctly, this is disabling ALL interrupts (except NMI & faults) so the timer used to wake the processor doesn’t get it’s interrupt handled until "
" is called later. HOWEVER, the comments indicate that the quoted code will somehow mask off fewer interrupts than
. I looked at the code involved there, and it just changes the BASEPRI register to some intermediate value, which, if I understand correctly, will mask off interrupts with lower priority (higher numeric value on a CM3) than BASEPRI, but not all interrupts (unless it is set to zero).
Am I missing something or are these comments not applicable and misleading?